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| 1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003-2004, zarlink semiconductor inc. all rights reserved. features ? ntegrated single-chip 10/100/1000 mbps ethernet switch ? 16 10/100 mbps autosensing, fast ethernet ports with rmii or serial interface (7ws). each port can independently use one of the two interfaces. ? 2 gigabit ports with gm ii, pcs, 10/100 options per port ? serial cpu interface for configuration ? supports two frame buffer memory domains with sram at 100 mhz ? supports memory size 2 mb, or 4 mb ? applies centralized shared memory architecture ? up to 64 k mac addresses ? maximum throughput is 3.6 gbps non-blocking ? high performance packet forwarding (10.712 m packets per second) at full wire speed ? full duplex ethernet ieee 802.3x flow control ? backpressure flow control for half duplex ports ? supports ethernet multicasting and broadcasting and flooding control ? supports per-system option to enable flow control for best effort frames even on qos-enabled ports ? traffic classification ? 4 transmission priorities for fast ethernet ports with 2 dropping levels ? classification based on: - port based priority - vlan priority field in vlan tagged frame - ds/tos field in ip packet - udp/tcp logical ports: 8 hard-wired and 8 programmable ports, including one programmable range ? the precedence of the above classifications is programmable february 2004 ordering information ZL50417/gkc553 pin hsbga -40 c to +85 c figure 1 - system block diagram fdb interface frame data buffer a sram (1 m / 2 m) led search engine mct link frame engine fcb management module 16 x 10 /100 rmii ports 0 - 15 vlan 1 mct frame data buffer b sram (1 m / 2 m) vlan 1 mct gmii/ port 0 pcs gmii/ port 1 pcs ZL50417 unmanaged 16-port 10/100 m + 2-port 1 g ethernet switch data sheet
ZL50417 data sheet 2 zarlink semiconductor inc. ? qos support ? supports ieee 802.1p/q quality of serv ice with 4 transmission priority queues with delay bounded, strict priority, and wfq service disciplines ? provides 2 levels of dropping precedence with wred mechanism ? user controls the wred thresholds ? buffer management: per class and per port buffer reservations ? port-based priority: vlan priority in a tagged frame c an be overwritten by the pr iority of port vlan id. ? 3 port trunking groups, one for the 2 gigabit ports, and two groups for 10/100 ports, with up to 4 10/100 ports per group. or 8 groups for 10/100 ports with up to 2 10/100 ports per group. ? load sharing among trunked ports can be based on source mac and/or destination mac. the gigabit trunking group has one more option, based on source port. ? port mirroring to a d edicated mirroring port ? full set of led signals provided by a serial interface, or 6 led signals dedicated to gigabit port status only (without serial interface) ? hardware auto-negotiation through serial management interface (mdio) for ethernet ports ? built-in reset logic trigge red by system malfunction ? built-in self test for internal and external sram ? i2c eeprom for configuration ? 553 bga package ZL50417 data sheet 3 zarlink semiconductor inc. description the ZL50417 is a high density, low cost, high perfo rmance, non-blocking ethernet switch chip. a single chip provides 16 ports at 10/100 mbps, 2 ports at 1000 mbps. the gigabit ports can also support 10/100 m. the chip supports up to 64 k mac addresses. the centra lized shared memory archit ecture permits a very high performance packet forwarding rate at up to 5.357 m packets per second at full wire speed. the chip is optimized to provide low-cost, high-performance workgroup switching. two frame buffer memory domains utilize cost-effecti ve, high-performance synchronous sram with aggregate bandwidth of 12.8 gbps to support full wire speed on all ports simultaneously. with delay bounded, strict priority, and/or wfq tran smission scheduling, and wred dropping schemes, the ZL50417 provides powerful qos functions for various multimedia and mission-critical applications. the chip provides 4 transmission priorities (8 priorities per gigabit port) and 2 levels of dropping precedence. each packet is assigned a transmission priority and dropping precedence based on the vlan priority field in a vlan tagged frame, or the ds/tos field, and udp/tcp logical port fi elds in ip packets. the ZL50417 recognizes a total of 16 udp/tcp logical ports, 8 hard-wired and 8 programmable (including one programmable range). the ZL50417 supports 3 groups of port trunking/load sharin g. one group is dedicated to the two gigabit ports, and the other two groups to 10/100 ports, wh ere each 10/100 group can contain up to 4 ports. port trunking/load sharing can be used to group ports between interlinked swit ches to increase the effective network bandwidth. in half-duplex mode, all ports support backpressure flow c ontrol, to minimize the risk of losing data during long activity bursts. in full-dupl ex mode, ieee 802.3x flow control is prov ided. the ZL50417 also supports a per-system option to enable flow control for best effort frames, even on qos-enabled ports. the physical coding sublayer (pcs) is integrated on-chip to provide a direct 10-bit interface for connection to serdes chips. the pcs can be bypassed to provide a gmii interface. the ZL50417 is fabricated using 0.25 micron technology . inputs, however, are 3.3 v tolerant, and the outputs are capable of directly interfacing to lvttl levels. the ZL50417 is packaged in a 553-pin ball grid array package. zl50416 data sheet table of contents 4 zarlink semiconductor inc. 1.0 block functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 frame data buffer (fdb) interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 gmii/pcs mac module (gmac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3 physical coding sublayer (pcs) interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.4 10/100 mac module (rmac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.5 configuration interface module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.6 frame engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.7 search engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.8 led interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.9 internal memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.0 system configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 configuration mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 i2c interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.1 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.2 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.3 data direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.4 acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.5 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.6 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 synchronous serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.1 write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.2 read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.0 ZL50417 data forwarding protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 unicast data frame forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 multicast data frame forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.0 memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.2 detailed memory information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 memory requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.0 search engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 search engine overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 basic flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3 search, learning, and aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3.1 mac search. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3.2 learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.3.3 aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4 quality of service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.5 priority classification rule. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.6 port-based vlan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.7 memory configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.0 frame engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1 data forwarding summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.2 frame engine details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.2.1 fcb manager. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.2.2 rx interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.2.3 rxdma. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.2.4 txq manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.3 port control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.4 txdma. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.0 quality of service and flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.1 model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 zl50416 data sheet table of contents 5 zarlink semiconductor inc. 7.2 four qos configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.3 delay bound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.4 strict priority and best effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.5 weighted fair queuing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.6 shaper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.7 wred drop threshold management suppor t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.8 buffer management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.8.1 dropping when buffers are scarce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.9 ZL50417 flow control basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.9.1 unicast flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.9.2 multicast flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.10 mapping to ietf diffserv classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.0 port trunking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.1 features and restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.2 unicast packet forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.3 multicast packet forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.4 trunking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.0 port mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.1 port mirroring features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.2 setting registers for port mirroring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.0 tbi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.1 tbi connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11.0 gpsi (7ws) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11.1 gpsi connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11.2 scan link and scan col interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 12.0 led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.1 led interface introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.2 port status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12.3 led interface timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 13.0 register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 13.1 ZL50417 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 13.2 (group 0 address) mac ports group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 13.2.1 ecr1pn: port n control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 13.2.2 ecr2pn: port n control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 13.2.3 ggcontrol ? extra giga port control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 13.3 (group 1 address) vlan group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 13.3.1 avtcl ? vlan type code register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 13.3.2 avtch ? vlan type code register high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 13.3.3 pvmap00_0 ? port 00 configuration register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 13.3.4 pvmap00_1 ? port 00 configuration register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 13.3.5 pvmap00_3 ? port 00 configuration register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 13.4 port configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.4.1 pvmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 13.5 (group 2 address) port trunking grou ps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.5.1 trunk0_mode? trunk group 0 mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.5.2 trunk1_mode ? trunk group 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 13.5.3 trunk2_mode ? trunk group 2 mode (gigabit ports 1 an d 2). . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.5.4 rqss ? receive queue status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 13.6 (group 4 address) search engine grou p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 13.6.1 agetime_low ? mac address aging time low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 13.6.2 agetime_high ?mac addr ess aging time high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 zl50416 data sheet table of contents 6 zarlink semiconductor inc. 13.6.3 se_opmode ? search engi ne operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 13.7 (group 5 address) buffer control/qos group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 13.7.1 fcbat ? fcb aging timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 13.7.2 qosc ? qos control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 13.7.3 fcr ? flooding control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 13.7.4 avpml ? vlan priority map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 13.7.5 avpmm ? vlan priority ma p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 13.7.6 avpmh ? vlan priority map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 13.7.7 tospml ? tos priority map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 13.7.8 tospmm ? tos priority map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 13.7.9 tospmh ? tos priority map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 13.7.10 avdm ? vlan discard map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 13.7.11 tosdml ? tos discard map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 13.7.12 bmrc - broadcast/multicast rate control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 13.7.13 ucc ? unicast congestion control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 13.7.14 mcc ? multicast congestion control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 13.7.15 pr100 ? port reservation for 10/100 ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 13.7.16 prg ? port reservation for giga port s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 13.7.17 sfcb ? share fcb size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 13.7.18 c2rs ? class 2 reserve size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 13.7.19 c3rs ? class 3 reserve size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 13.7.20 c4rs ? class 4 reserve size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 13.7.21 c5rs ? class 5 reserve size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 13.7.22 c6rs ? class 6 reserve size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 13.7.23 c7rs ? class 7 reserve size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 13.7.24 qoscn - classes byte limit set 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 13.7.25 classes byte limit set 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 13.7.26 classes byte limit set 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 13.7.27 classes byte limit set 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 13.7.28 classes byte limit giga port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 13.7.29 classes byte limit giga port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 13.7.30 classes wfq credit set 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 13.7.31 classes wfq credit set 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 13.7.32 classes wfq credit set 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 13.7.33 classes wfq credit set 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 13.7.34 classes wfq credit port g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 13.7.35 classes wfq credit port g2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 13.7.36 class 6 shaper control port g1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 13.7.37 class 6 shaper control port g2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 13.7.38 rdrc0 ? wred rate control 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 13.7.39 rdrc1 ? wred rate control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 13.7.40 user defined logical ports and well known ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 13.7.40.1 user_port0_(0~7) ? user define logical port (0 ~7). . . . . . . . . . . . . . . . . . . . . . . . . . . 68 13.7.40.2 user_port_[1:0]_priority - user define logic port 1 and 0 pr iority . . . . . . . . . . . . . 68 13.7.40.3 user_port_[3:2]_priority - user define logic port 3 and 2 pr iority . . . . . . . . . . . . . 69 13.7.40.4 user_port_[5:4]_priority - user define logic port 5 and 4 pr iority . . . . . . . . . . . . . 69 13.7.40.5 user_port_[7:6]_priority - user define logic port 7 and 6 pr iority . . . . . . . . . . . . . 69 13.7.40.6 user_port_enable[7:0] ? user define logic 7 to 0 port enables . . . . . . . . . . . . . . . 69 13.7.40.7 well_known_port[1:0] priority- well known logic port 1 and 0 priority . . . . . . . 70 13.7.40.8 well_known_port[3:2] priority- well known logic port 3 and 2 priority . . . . . . . 70 13.7.40.9 well_known_port [5:4] priority- well k nown logic port 5 and 4 priority . . . . . . 70 13.7.40.10 well_known_port [7:6] priority- well known logic port 7 and 6 priority . . . . . 70 zl50416 data sheet table of contents 7 zarlink semiconductor inc. 13.7.40.11 well known_port_enable [7:0] ? well known logic 7 to 0 port enables. . . . . . . 71 13.7.40.12 rlowl ? user define range lo w bit 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 13.7.40.13 1rlowh ? user define range low bit 15:8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 13.7.40.14 rhighl ? user define range high bit 7:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 13.7.40.15 rhighh ? user define range high bit 15:8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 13.7.40.16 rpriority ? user define range priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 13.8 (group 6 address) misc group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 13.8.1 mii_op0 ? mii register option 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 13.8.2 mii_op1 ? mii register option 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 13.8.3 fen ? feature register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 13.8.4 miic0 ? mii co mmand register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 13.8.5 miic1 ? mii co mmand register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 13.8.6 miic2 ? mii co mmand register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 13.8.7 miic3 ? mii co mmand register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 13.8.8 miid0 ? mii data re gister 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 13.8.9 miid1 ? mii data re gister 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 13.8.10 led mode ? led control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 13.8.11 checksum - eeprom checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 13.9 (group 7 address) port mirroring group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 13.9.1 mirror1_src ? port mirror source port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 13.9.2 mirror1_dest ? port mirror destination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 13.9.3 mirror2_src ? port mirror source port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 13.9.4 mirror2_dest ? port mirror destination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 13.10 (group f address) cpu access group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 13.10.1 gcr-global control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 13.10.2 dcr-device status and signature register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 13.10.3 dcr1-giga port status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 13.10.4 dpst ? device port status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 13.10.5 dtst ? data read back register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 13.10.6 pllcr - pll control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 13.10.7 lclk - la_clk delay from internal oe_clk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 0 13.10.8 oeclk - internal oe_clk delay from sclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.10.9 da ? da register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.11 tbi registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 13.11.1 control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 13.11.2 status register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 13.11.3 advertisement register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 13.11.4 link partner ability register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 13.11.5 expansion register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 13.11.6 extended status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 14.0 bga and ball signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 14.1 bga views (top-view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 14.1.1 ball signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 14.2 ball signal name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 14.3 ac/dc timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 14.3.1 absolute maxi mum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 14.3.2 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 14.3.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 14.3.4 typical reset & bootstrap timing di agram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 14.4 local frame buffer sbram memory inte rface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 14.4.1 local sbram memory interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 14.5 local switch database sbram memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 zl50416 data sheet table of contents 8 zarlink semiconductor inc. 14.5.1 local sbram memory interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 14.6 ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 14.6.1 reduced media independent interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 14.6.2 gigabit media independent interface - port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 14.6.3 ten bit interface - port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 14.6.4 gigabit media independent interface - port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 14.6.5 ten bit interface - port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 14.6.6 led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 14.6.7 scanlink scancol output delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 14.6.8 mdio input setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 14.6.9 i2c input setup timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 14.6.10 serial interface setup timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 ZL50417 data sheet list of tables 9 zarlink semiconductor inc. table 1 - supported memory configurations (pipeline sbram mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 2 - options for memory configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 3 - two-dimensional world traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 4 - four qos configurations for a 10/100 mbps port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 5 - four qos configurations for a gigabit port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 6 - mapping between ZL50417 and ietf diffserv classes for gigabit ports . . . . . . . . . . . . . . . . . . . . . . . . 32 table 7 - mapping between ZL50417 and ietf diffserv classes fo r 10/100 ports . . . . . . . . . . . . . . . . . . . . . . . . 33 table 8 - ZL50417 features enabling ietf diffserv standards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 9 - select via trunk0_mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 10 - select via trunk1_mode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 11 - individually enabled/disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 12 - reset & bootstrap timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 13 - output delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 14 - input setup timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 15 - output delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 16 - input setup timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 17 - ac characteristics ? led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 18 - scanlink, scancol timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 table 19 - mdio timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 20 - i2c timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 21 - serial interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 ZL50417 data sheet list of figures 10 zarlink semiconductor inc. figure 1 - system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - data transfer format for i2c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 3 - write command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4 - read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5 - ZL50417 sram interface block diagram (dmas for 10/1 000 ports only) . . . . . . . . . . . . . . . . . . . . . . 16 figure 6 - memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7 - priority classification rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 8 - memory configuration for: 2 banks, 1 layer, 2 mb to tal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 9 - memory configuration for: 2 banks, 2 layers, 4 mb to tal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 10 - memory configuration for: 2 banks, 1 layer, 4 mb tota l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 11 - summary of the behaviour of the wred logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 12 - buffer partition scheme used to implement buffer management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 13 - tbi connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 14 - gpsi (7ws) mode connection diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 15 - scan link and scan collison status diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 16 - timing diagram of led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 17 - typical reset & bootstrap timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 18 - local memory interface ? input setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 19 - local memory interface - output valid delay timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 20 - local memory interface ? input setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 21 - local memory interface - output valid delay timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 22 - ac characteristics ? reduced media independent interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 23 - ac characteristics ? reduced media independent interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 24 - ac characteristics- gmii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 25 - ac characteristics ? gigabit media independent interf ace. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 26 - gigabit tbi interface transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 27 - gigabit tbi interface receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 28 - ac characteristics- gmii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 29 - ac characteristics ? gigabit media independent interf ace. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 30 - gigabit tbi interface transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 31 - gigabit tbi interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 32 - ac characteristics ? led interf ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 33 - scanlink scancol output delay timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 34 - scanlink, scancol setup timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 35 - mdio input setup and hold timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 36 - mdio output delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 37 - i2c input setup timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 38 - i2c output delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 39 - serial interface setu p timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 40 - serial interface output delay timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 ZL50417 data sheet 11 zarlink semiconductor inc. 1.0 blo ck functionality 1.1 frame data buffer (fdb) interfaces the fdb interface supports pipelined synchronous burst sram (sbram) memory at 100 mhz. to ensure a non- blocking switch, two memory domains are required. each domain has a 64-bit wide memory bus. at 100 mhz, the aggregate memory bandwidth is 12.8 gbps, which is enough to support 16 10/100 mbps and 2 gigabit ports at full wire speed switching. the switching database is also located in the external sram; it is used for storing mac addresses and their physical port number. it is duplicated and stored in both memory domains. therefore, when the system updates the contents of the switching database, it has to wr ite the entry to both domains at the same time. 1.2 gmii/pcs mac module (gmac) the gmii/pcs media access control (mac) module provides the necessary buffers and control interface between the frame engine (fe) and the external physical device (phy). the ZL50417 gmac implements both gmii and mii interfac e, which offers a simple migration from 10/100 to 1 g. the gmac of the zl504 17 meets the ieee 802.3z specific ation. it is able to operat e in 10m/100 m either half or full duplex mode with a back pressure/flow control mechanism or in 1 g full duplex mode with flow control mechanism. furthermore, it will automatically retransmit upon collision for up to 16 total transmissions. phy addresses for gmac are 01h and 02h. for fiber optics media, the ZL50417 implements the physical code sublayer (pcs) interface. the pcs includes an 8b10b encoder and decoder, auto-negot iation, and ten bit interface (tbi). 1.3 physical coding sublayer (pcs) interface for the ZL50417, the 1000base-x pcs interface is designed internally and may be utili zed in the absence of a gmii. the pcs incorporates all the functions required by the gmii to include encoding (decoding) 8b gmii data to (from) 8b/10b tbi format for phy commu nication and generating collision detect (col) signals for half-duplex mode. it also manages the auto negotiation process by in forming the management entity that the phy is ready for communications. the on-chip tbi may be disabled if tbi exists within the gigabit phy. the tbi interface provides a uniform interface for all 1000 mbps phy implementations. the pcs comprises the pcs transmit, synchronization, pcs receive, and auto negotiation processes for 1000base-x. the pcs transmit process sends the tbi signals txd [9:0] to the physi cal medium and generates the gmii collision detect (col) signal based on whether a reception is occurring simultaneously with transmission. additionally, the transmit process generates an internal ?transmitting? flag and monitors auto negotiation to determine whether to transmit data or to reconfigure the link. the pcs synchronization process determines whether or not the receive channel is operational. the pcs receive process generates rxd [7:0] on the gmii fr om the tbi data [9:0], and th e internal ?receiving? flag for use by the transmit processes. the pcs auto negotiation process allows the ZL50417 to exchange configuration information between two devices that share a link segment, and to au tomatically configure the link for the appropriate speed of operation for both devices. ZL50417 data sheet 12 zarlink semiconductor inc. 1.4 10/100 mac module (rmac) the 10/100 media access control module provides the ne cessary buffers and control interface between the frame engine (fe) and the external physical device (phy). the ZL50417 has two interfaces, rmii or serial (only for 10 m). the 10/100 mac of the ZL50417 device meets the ieee 802.3 specification. it is able to oper ate in either half or full duplex mode with a back pressure/flow contro l mechanism. in addition, it will automatically retransmit upon collision for up to 16 total transmissions. the phy addresses for 16 10/100 mac are from 08h to 1fh. 1.5 configuration interface module the ZL50417 supports a serial and an i2c interface, which provides an easy way to confi gure the system. once configured, the re sulting configuration can be stored in an i2c eeprom. 1.6 frame engine the main function of the frame engine is to forward a fram e to its proper destination po rt or ports. when a frame arrives, the frame engine parses the frame header (64 by tes) and formulates a switching request, which is sent to the search engine to resolve the destination port. the arri ving frame is moved to the fdb. after receiving a switch response from the search engine, the frame engine perf orms transmission scheduling based on the frame?s priority. the frame engine forwards the frame to the mac module when the frame is ready to be sent. 1.7 search engine the search engine resolves the frame?s destination port or ports according to the destination mac address (l2) or ip multicast address (ip multicast packet) by searching the database. it also performs mac learning, priority assignment, and trunking functions. 1.8 led interface the led interface provides a serial interface for carrying 16 + 2 port status signals. it can also provide direct status pins (6) for the two gigabit ports. 1.9 internal memory several internal tables are required and are described as follows: ? frame control block (fcb) - each fcb entry contains the control information of the associated frame stored in the fdb, e.g,. frame si ze, read/write pointer, tr ansmission priority, etc. ? mct link table - the mct link table stores the linked li st of mct entries that have collisions in the external mac table. the external mac table is located in the fdb memory. note that the external mac table is located in the external ssram memory. 2.0 system configuration 2.1 configuration mode the ZL50417 can be confi gured by eeprom (24c02 or co mpatible) via an i2c interfac e at boot time, or via a synchronous serial interface during operation. 2.2 i 2 c interface the i2c interface uses two bus lines, a serial data line (sda ) and a serial clock line (scl). the scl line carries the control signals that facilitate the transfe r of information from eeprom to the switch. data transf er is 8-bit serial and bidirectional, at 50 kbps. data transfer is perf ormed between master and slave ic using a request / ZL50417 data sheet 13 zarlink semiconductor inc. acknowledgment style of protocol. the master ic generates the timing signals and terminates data transfer. figure 2 depicts the data transfer format. figure 2 - data transfer format for i2c interface 2.2.1 start condition generated by the master (in our case, the ZL50417). the bus is considered to be busy after the start condition is generated. the start condition occurs if while the scl line is high, there is a high-to-low transition of the sda line. other than in the start condition (and stop condition), the data on the sda line must be stable during the high period of scl. the high or low state of sda can only change when scl is low. in addition, when the i2c bus is free, both lines are high. 2.2.2 address the first byte after the start condition determines which sl ave the master will select. th e slave in our case is the eeprom. the first seven bits of the first data byte ma ke up the slave address. 2.2.3 data direction the eighth bit in the first byte after the start conditi on determines the direction (r /w) of the message. a master transmitter sets this bit to w; a master receiver sets this bit to r. 2.2.4 acknowledgment like all clock pulses, the acknowledgment-related clock pul se is generated by the master. however, the transmitter releases the sda line (high) during the acknowledgment cl ock pulse. furthermore, the receiver must pull down the sda line during the acknowledge pulse so that it remains stable low during the high period of this clock pulse. an acknowledgment pulse follows every byte transfer. if a slave receiver does not acknowledge after any byte, t hen the master generates a stop condition and aborts the transfer. if a master receiver does not acknowledge after any byte , then the slave transmitter must release the sda line to let the master generate the stop condition. 2.2.5 data after the first byte containing the address, all bytes that follow are data bytes. each byte must be followed by an acknowledge bit. data is transferred msb first. 2.2.6 stop condition generated by the master. the bus is cons idered to be free after the stop condition is generated. the stop condition occurs if while the scl line is high, there is a low-to-high transition of the sda line. the i2c interface serves the function of configuring the ZL50417 at boot time . the master is the ZL50417, and the slave is the eeprom memory. start slave address r/w ack data 1 (8 bits) ack data2 ack datam ack stop ZL50417 data sheet 14 zarlink semiconductor inc. 2.3 synchronous serial interface the synchronous serial interface serves the function of co nfiguring the ZL50417 not at boot time but via a pc. the pc serves as master and the ZL50417 serves as slave. th e protocol for the synchronous serial interface is nearly identical to the i2c protocol. the main difference is that there is no acknowledgment bit after each byte of data transferred. the unmanaged ZL50417 uses a synchronous serial interface to program the internal registers. to reduce the number of signals required, the register address, command and data are shifted in serially through the d0 pin. strobe- pin is used as the shift clock. autofd- pin is used as data return path. each command consis ts of four parts. ?start pulse ? register address ? read or write command ? data to be written or read back any command can be aborted in the middle by sending a abort pulse to the ZL50417. a start command is detected when d0 is sampled high when strobe- rise and d0 is sampled low when strobe- fall. an abort command is detected when d0 is sampled low when strobe- rise and d0 is sampled high when strobe- fall. 2.3.1 write command figure 3 - write command 2.3.2 read command figure 4 - read command strobe- d0 a0 a2 ... a9 a10 a11 a1 w d0 d1 d2 d3 d4 d5 d6 d7 start address command data 2 extra clocks after last transfer strobe- d0 autofd- a0 a1 a2 ... a9 a10 a11 r d0 d1 d2 d3 d4 d5 d6 d7 start address command data ZL50417 data sheet 15 zarlink semiconductor inc. all registers in ZL50417 can be modified through this synchronous serial interface. 3.0 ZL50417 data forwarding protocol 3.1 unicast data frame forwarding when a frame arrives, it is assigned a handle in memo ry by the frame control buffer manager (fcb manager). an fcb handle will always be available, because of advance buffer reservations. the memory (sram) interface is two 64-bit buses, connected to two sram banks, a and b. the receive dma (rxdma) is responsible for multiplexing the data and the address. on a port?s ?turn,? the rxdma will move 8 bytes (or up to the end-of-frame) from th e port?s associated rxfifo into memo ry (frame data buffer, or fdb). once an entire frame has been moved to the fdb, and a good end-of-frame (eof) has been received, the rx interface makes a switch request. the rxdma arbitrates among multiple switch requests. the switch request consists of the first 64 bytes of a frame, containing among other things, the source and destination mac addresses of the frame. the search engi ne places a switch response in the switch response queue of the frame engine when done. among other in formation, the search engine will have resolved the destination port of the frame and will have determined that the frame is unicast. after processing the switch response, the transmission queue manager (txq manager) of the frame engine is responsible for notifying the destination port that it has a frame to forward to it. bu t first, the txq manager has to decide whether or not to drop the frame, based on globa l fdb reservations and usage, as well as txq occupancy at the destination. if the frame is not dropped, then the txq manager links the frame?s fcb to the correct per-port- per-class txq. unicast txq?s are linked lists of transmi ssion jobs, represented by their associated frames? fcb?s. there is one linked list for each transmission class for eac h port. there are 4 transmission classes for each of the 16 10/ 100 ports, and 8 classes for each of the two gigabit ports ? a total of 112 unicast queues. the txq manager is responsible for scheduling transmission among the queues representing different classes for a port. when the port control module determines that ther e is room in the mac transmission fifo (txfifo) for another frame, it requests the handle of a new frame from the txq manager. the txq manager chooses among the head-of-line (hol) frames from the per-class queues for that port, using a zarlink semiconductor scheduling algorithm. the transmission dma (txdma) is responsible for multiplexing the data and the address. on a port?s turn, the txdma will move 8 bytes (or up to the eof) from memory into the port?s associated txfifo. after reading the eof, the port control requests a fcb release for that frame. the txdma arbitrates among multiple buffer release requests. the frame is transmitted from the txfifo to the line. 3.2 multicast data frame forwarding after receiving the switch re sponse, the txq manager has to make the dropping decision. a global decision to drop can be made, based on global fdb utilization and reservat ions. if so, then the fcb is released and the frame is dropped. in addition, a selective decision to drop can be made, based on the txq occupancy at some subset of the multicast packet?s destinations. if so, then the frame is dropped at some destinations but not others, and the fcb is not released. if the frame is not dropped at a particular destination po rt, then the txq manager formats an entry in the multicast queue for that port and class. multicast queues are physi cal queues (unlike the linked lists for unicast frames). there are 2 multicast queues for each of the 16 10/100 ports. the queue with higher priority has room for 32 entries and the queue with lower priority has room for 64 entries. there are 4 multicast queues for each of the two gigabit ports. the size of the queues are: 32 entries (higher priori ty queue), 32 entries, 32 entries and 64 entries (lower priority queue). there is one multicast queue for every two priority classes. for the 10/100 ports to map the 8 ZL50417 data sheet 16 zarlink semiconductor inc. transmit priorities into 2 multicast queues, the 2 lsb are discarded. for the gigabit ports to map the 8 transmit priorities into 4 multicast queues, the lsb are discarded. during scheduling, the txq manager treats the unicast qu eue and the multicast queue of the same class as one logical queue. the older head of line of the two queues is forwarded first. the port control requests a fcb release only after the eo f for the multicast frame has been read by all ports to which the frame is destined. 4.0 memory interface 4.1 overview the ZL50417 provides two 64-bit-wide sram banks, sr am bank a and sram bank b, with a 64-bit bus connected to each. each dma can read and write from both bank a and bank b. the following figure provides an overview of the ZL50417 sram banks. figure 5 - ZL50417 sram interface block diagram (dmas for 10/1000 ports only) 4.2 detailed memory information because the bus for each bank is 64-bits wide, frames ar e broken into 8-byte granules, written to and read from memory. the first 8-byte granule gets written to bank a, the second 8-byte granule gets written to bank b and so on in alternating fashion. when reading frames from memory, th e same procedure is followed, first from a, then from b and so on. the reading and writing from alternating memory banks can be performed with minimal waste of memory bandwidth. what?s the worst case? for any speed port, in the worst case, a 1-byte-long eof granule gets written to bank a. this means that a 7-byte segment of bank a bandwidth is idle, and furthermore, the next 8-byte segment of bank b bandwidth is idle, because the first 8 by tes of the next frame will be written to bank a, not b. this scenario results in a maximum 15 bytes of waste per frame, which is always acceptable because the interframe gap is 20 bytes. sram bank a txdma 0-7 txdma 8-15 rxdma 0-7 rxdma 8-15 sram bank b ZL50417 data sheet 17 zarlink semiconductor inc. 4.3 memory requirements to speed up searching and decrease memory latency, th e external mac address database is duplicated in both memory banks. to support 64 k mac address, 4 mb memo ry is required. when vlan support is enabled, 512 entries of the mac address table are used for stor ing the vlan id at vlan index mapping table. up to 2 k ethernet frame buffers are supported and they will use 3 mb of memory. each frame uses 1536 bytes. the maximum system memory re quirement is 4 mb. if less memory is des ired, the configurat ion can scale down. memory configuration memory map figure 6 - memory map bank a bank b tag based vlan frame buffer max mac address 1m 1m disable 1k 32k 1m 1m enable 1k 31.5k 2m 2m disable 2k 64k 2m 2m enable 2k 63.5k 1 m bank a 1 m bank b 2 m bank a 2 m bank b 0.75 m 0.75 m 1.5 m 1.5 m 0.25 m 0.25 m 0.5 m 0.5 m tag based vlan disable 1 m bank a 1 m bank b 2 m bank a 2 m bank b 0.7 5 m 0.75 m 1.5 m 1.5 m 0.25 m ? 4 k 0.25 m 0.5 m ? 4 k 0.5 m 4 k 4 k 4 k 4 k tag based vlan enable frame data buffer (fdr) area mac address control table (mct) area vlan table area ZL50417 data sheet 18 zarlink semiconductor inc. 5.0 search engine 5.1 search engine overview the ZL50417 search engine is optimized for high throughput searching, with enhanced features to support: ? up to 64 k mac addresses ? up to 255 vlan and ip multicast groups ? 3 groups of port trunking (1 for the two gigabit ports, and 2 others) ? traffic classification into 4 (or 8 for gigabit) transmission priorities, and 2 drop precedence levels ? packet filtering ? security ?ip multicast ? flooding, broadcast, multicast storm control ? mac address learning and aging 5.2 basic flow shortly after a frame enters the ZL50417 and is written to the frame data buffer (fdb), the frame engine generates a switch request, which is sent to the search engine. the switch request consists of t he first 64 bytes of the frame, which contain all the necessary information for the search engine to perform its task. when the search engine is done, it writes to the switch response queue, and the frame engine uses the information provided in that queue for scheduling and forwarding. in performing its task, the search engine extracts and compresses the useful information from the 64-byte switch request. among the information extracted are the source and destination mac addresses, the transmission and discard priorities, whether the frame is unicast or multicas t, and vlan id. requests are sent to the external sram to locate the associated entries in the external hash table. when all the information has been collected from external sram, the search engine has to compare the mac address on the current entry with the mac address for which it is searching. if it is not a match, the process is repeated on the internal mct table. all mct entries other than the first of each linked list are maintained internal to the chip. if the desired mac address is still not found, t hen the result is either learning (source mac address unknown) or flooding (destination mac address unknown). in addition, port based vlan information is used to sele ct the correct set of destination ports for the frame (for multicast), or to verify that the frame?s destination port is a ssociated with the vlan (for unicast). if the destination mac address belongs to a port trunk, then the trunk number is retrieved instead of the port number. but on which port of the trunk will the frame be transmitted? this is easily computed using a hash of the source and destination mac addresses. as stated earlier, when all th e information is comp iled the switch resp onse is generated. 5.3 search, learning, and aging 5.3.1 mac search the search block performs source mac address and dest ination mac address searching. as we indicated earlier, if a match is not found, then the next entry in the linked list must be examined, and so on until a match is found or the end of the list is reached. ZL50417 data sheet 19 zarlink semiconductor inc. in port based vlan mode, a bitmap is used to determi ne whether the frame should be forwarded to the outgoing port. when the egress port is not included in the ingress port vlan bitmap, the packet is discarded. the mac search block is also responsible for updating the source mac address timestamp and the vlan port association timestamp, used for aging. 5.3.2 learning the learning module learns new mac addresses and per forms port change operations on the mct database. the goal of learning is to update this database as the networking environment changes over time. 5.3.3 aging aging time is controlled by register 400h and 401h. the aging module scans and ages mct entries based on a programmable ?age out? time interval. as we indicated earlier, the search module updates the source mac address timestamps for each frame it processes. when an entry is ready to be aged, the entry is removed from the table. 5.4 quality of service quality of service (qos) refers to the ability of a network to provide bett er service to selected network traffic over various technologies. primary goals of qos include dedicated bandwidth, controlled jitter and latency (required by some real-time and interactive traffi c), and improved loss characteristics. traditional ethernet networks have had no prioritization of tr affic. without a protocol to prioritize or differentiate traffic, a service level known as ?best effort? attempts to get all the packets to their intended destinations with minimum delay; however, there are no guarantees. in a congested network or when a low-performance switch/router is overloaded, ?best effort? becomes unsuitable for delay-sensitive traffic and mission-critical data transmission. the advent of qos for packet-based systems accommodates the integratio n of delay-sensitive video and multimedia traffic onto any existing ethernet network. it al so alleviates the congestion issues that have previously plagued such ?best effort? ne tworking systems. qos provides ethernet networks with the break through technology to prioritize traffic and ensure th at a certain transmission will have a guaranteed minimum amount of bandwidth. extensive core qos mechanisms are built into the zl 50417 architecture to ensure policy enforcement and buffering of the ingress port, as well as weighted fair-queue(wfq) scheduling at the egress port. in the ZL50417, qos-based policies sort traffic into a small number of classes and mark the packets accordingly. the qos identifier provides specific treatment to traffic in different classes, so that different quality of service is provided to each class. frame and packet scheduling and discarding policies are determined by the class to which the frames and packets belong. for example, the overall se rvice given to frames and packets in the premium class will be better than that given to the standard class; the premium class is expected to experience lower loss rate or delay. the ZL50417 supports the following qos techniques: in a port-based setup, any station connected to the same physical port of the switch will have the same transmit priority. in a tag-based setup, a 3-bit field in the vlan tag provides the priority of the packet. this priority can be mapped to different queues in the switch to provide qos. in a tos/ds-based set up, tos stands for ?type of service? that may include ?minimize delay,? ?maximize throughput,? or ?maximize reliability.? network nodes may select routing paths or forwarding behaviors that are suitably engineered to satisfy the service request. ZL50417 data sheet 20 zarlink semiconductor inc. in a logical port-based set up, a logical port provides the application information of the packet. certain applications are more sensitive to delays than others; using logical ports to classify packets can he lp speed up delay sensitive applications, such as voip. 5.5 priority classification rule figure 7 shows the ZL50417 priority classification rule. figure 7 - priority classification rule fix port priority ? yes yes yes yes yes yes no no no no no use tos use logical port use default port settings use vlan priority use default port settings tos precedence over vlan? vlan tag ? ip frame ? ip (fcr register, bit 7) no use logical port ZL50417 data sheet 21 zarlink semiconductor inc. 5.6 port-based vlan an administrator can use the pvmap registers to configur e the ZL50417 for port-based vlan (see ?registration definition? on page 42). for example, ports 1-3 might be assigned to the marketing vlan, ports 4-6 to the engineering vlan, and ports 7-9 to the administrative vlan. the ZL50417 determines the vlan membership of each packet by noting the port on which it arrives. from there, the ZL50417 determines which outgoing port(s) is/are eligible to transmit each packet, or whether the packet should be discarded. gigabit port 0 and 1 are denoted as port 25 and 26 respectively. for example, in the above table a 1 denotes that an outgo ing port is eligible to receive a packet from an incoming port. a 0 (zero) denotes that an outgoing port is not eligible to receive a packet from an incoming port. in this example: data packets received at port #0 are eligible to be sent to outgoing ports 1 and 2. data packets received at port #1 are eligible to be sent to outgoing ports 0 and 2. data packets received at port #2 are not eligible to be sent to ports 0 and 1. destination port numbers bit map port registers 18 ? 2 1 0 register for port #0 pvmap00_0[7:0] to pvmap00_3[2:0] 0110 register for port #1 pvmap01_0[7:0] to pvmap01_3[2:0] 0101 register for port #2 pvmap02_0[7:0] to pvmap02_3[2:0] 0000 ? register for port #18 pvmap26_0[7:0] to pvmap26_3[2:0] 0000 ZL50417 data sheet 22 zarlink semiconductor inc. 5.7 memory configurations the ZL50417 supports the following memory configurat ions. pipeline sbram modes support 1 m and 2m per bank configurations. for detail connection information, please reference the memory application note. configuration 1 m per bank (bootstrap pin tstout7 = open) 2 m per bank (bootstrap pin tstout7 = pull down) connections single layer (bootstrap pin tstout13 = open) two 128 k x 32 sram/bank or one 128 k x 64 sram/bank two 256 k x 32 sram/bank connect 0e# and we# double layer (bootstrap pin tstout13 = pull down) na four 128 k x 32 sram/bank or two 128 k x 64 sram/bank connect 0e0# and we0# connect 0e1# and we1# table 1 - supported memory configurations (pipeline sbram mode) only bank a bank a and bank b 1m (sram) 2m (sram) 1m/bank (sram) 2m/bank (sram) zl50415 x x zl50416 x x ZL50417 x x zl50418 x x table 2 - options for memory configuration ZL50417 data sheet 23 zarlink semiconductor inc. figure 8 - memory configuration for: 2 banks, 1 layer, 2 mb total figure 9 - memory configuration for: 2 banks, 2 layers, 4 mb total a ddress la_a[19:3] sram memory 128 k 32 bits memory 128 k 32 bits data la_d[63:32] data la_d[31:0] a ddress lb_a[19:3] sram memory 128 k 32 bits memory 128 k 32 bits data lb_d[63:32] data lb_d[31:0] bank a (1m one layer) bank b (1m one layer) bootstraps: tstout7 = open, tstout13 = open, tstout4 = open bank a (2m two layers) bank b (2m two layers) sram memory 128 k 32 bits sram memory 128 k 32 bits data lb_d[63:32] data lb_d[31:0] a ddress lb_a[19:3] sram memory 128 k 32 bits sram memory 128 k 32 bits sram memory 128 k 32 bits sram memory 128 k 32 bits data la_d[63:32] data la_d[31:0] a ddress la _ a[19:3] sram memory 128 k 32 bits sram memory 128 k 32 bits bootstraps: tstout7 = pull down, tstout13 = pull down, tstout4 = open ZL50417 data sheet 24 zarlink semiconductor inc. figure 10 - memory configuration for: 2 banks, 1 layer, 4 mb total 6.0 frame engine 6.1 data forwarding summary when a frame enters the device at the rxmac, the rx dma will move the data from the mac rxfifo to the fdb. data is moved in 8-byte granules in conjunction with the scheme for the sram interface. a switch request is sent to the search engine. the search engine processes the switch request. a switch response is sent back to the frame engine and indicates whether the frame is unicast or multicast, and its destination port or ports. a vlan table lookup is performed as well. a transmission scheduling request is sent in the form of a signal notifying the txq manager. upon receiving a transmission scheduling request, the device will format an entry in the appropriate transmission scheduling queue (txsch q) or queues. there are 4 txsch q for ea ch 10/100 port (and 8 per gigabit port), one for each priority. creation of a queue entry either involves linkin g a new job to the appropriate linked list if unicast, or adding an entry to a physical queue if multicast. when the port is ready to accept the next frame, the txq manager will get the head-of-line (hol) entry of one of the txsch qs, according to the transmission scheduling al gorithm (so as to ensure per-class quality of service). the unicast linked list and the multicast queue for the sa me port-class pair are treated as one logical queue. the older hol between the two queues goes first. for 10/100 ports multicast queue 0 is associated with unicast queue 0 and multicast queue 1 is associated wit h unicast queue 2. for gigabit ports multicast queue 0 is associated with unicast queue 0, multicast queue 1 with unicast queue 2, multicast queue 2 with unicast queue 4 and multicast queue 3 with unicast queue 6. the txdma will pull frame data from the memory and fo rward it granule-by-granule to the mac txfifo of the destination port. 6.2 frame engine details this section briefly describes the functions of each of the modules of the ZL50417 frame engine. a ddress la_a[20:3] sram memory 256 k 32 bits memory 256 k 32 bits data la_d[63:32] data la_d[31:0] a ddress lb_a[20:3] sram memory 256 k 32 bits memory 256 k 32 bits data lb_d[63:32] data lb_d[31:0] bank a (2m one layer) bank b (2m one layer) bootstraps: tstout7 = pull down, tstout13 = open, tstout4 = open ZL50417 data sheet 25 zarlink semiconductor inc. 6.2.1 fcb manager the fcb manager allocates fcb handles to incoming frames, and releases fcb handles upon frame departure. the fcb manager is also responsible for enforcing buffer reservations and limits. the default values can be determined by referring to chapter 7. in addition, the fcb manager is responsible for buffer aging, and for linking unicast forwarding jobs to their correct txsch q. the buffer aging can be enabled or disabled by the bootstrap pin and the aging time is defined in register fcbat. 6.2.2 rx interface the rx interface is mainly responsible for communicating with the rxmac. it keeps track of the start and end of frame and frame status (good or bad). upon receiving an en d of frame that is good, the rx interface makes a switch request. 6.2.3 rxdma the rxdma arbitrates among switch requests from each rx interface. it also buffers the first 64 bytes of each frame for use by the search engine when the switch request has been made. 6.2.4 txq manager first, the txq manager checks the per-c lass queue status and glob al reserved resource si tuation, and using this information, makes the frame dropping decision after receiving a switch response. if the decision is not to drop, the txq manager requests that the fcb manager link the unicast frame?s fcb to the correct per-port-per-class txq. if multicast, the txq manager writes to the multicast queu e for that port and class. the txq manager can also trigger source port flow control for the incoming frame?s sour ce if that port is flow co ntrol enabled. second, the txq manager handles transmission scheduling; it schedules transmission among the queues representing different classes for a port. once a frame has been scheduled, the txq manager reads the fcb information and writes to the correct port control module. 6.3 port control the port control module calculates the sram read address fo r the frame currently being tr ansmitted. it also writes start of frame information and an end of frame flag to the mac txfifo. when transmission is done, the port control module requests that the buffer be released. 6.4 txdma the txdma multiplexes data and address from port control, and arbitrates among buffer release requests from the port control modules. ZL50417 data sheet 26 zarlink semiconductor inc. 7.0 quality of se rvice and flow control 7.1 model quality of service is an all-encompassing term for which di fferent people have different interpretations. in general, the approach to quality of service described here assumes that we do not know the offered traffic pattern. we also assume that the incoming traffic is not policed or shaped. furthermore, we assume that the network manager knows his applications, such as voice, file transfer, or web browsing, and their relative importance. the manager can then subdivide the applications into classes and set up a service contract with each. the contract may consist of bandwidth or latency assurances per class. sometimes it may even reflect an estimate of the traffic mix offered to the switch. as an added bonus, although we do not assume anything about the arrival pattern, if the incoming traffic is policed or shaped, we may be able to provide addi tional assurances about our switch?s performance. table 3 shows examples of qos applications with three transm ission priorities, but best effort (p0) traffic may form a fourth class with no bandwidth or latency assurances. gigabit ports actually have eight total transmission priorities. a class is capable of offering traffic that exceeds the contracted bandwidth. a well-behaved class offers traffic at a rate no greater than the agreed-upon rate. by contrast, a misbehaving class offers traffic that exceeds the agreed- upon rate. a misbehaving class is formed from an aggreg ation of misbehaving microflows. to achieve high link utilization, a misbehaving class is allowed to use any idle bandwidth. however, such leniency must not degrade the quality of service (qos) received by well-behaved classes. as table 3 illustrates, the six traffic types may each have their own distinct properties and applications. as shown, classes may receive bandwidth assurances or latency bounds. in the table, p3, the highest transmission class, requires that all frames be transmitted within 1 ms, and receives 50% of the 100 mbps of bandwidth at that port. goals total assured bandwidth (user defined) low drop probability (low-drop) high drop probability (high-drop) highest transmission priority, p3 50 mbps apps: phone calls, circuit emulation. latency: < 1 ms. drop: no drop if p3 not oversubscribed. apps: training video. latency: < 1 ms. drop: no drop if p3 not oversubscribed; first p3 to drop otherwise. middle transmission priority, p2 37.5 mbps apps: interactive apps, web business. latency: < 4-5 ms. drop: no drop if p2 not oversubscribed. apps: non-critical interactive apps. latency: < 4-5 ms. drop: no drop if p2 not oversubscribed; firstp2 to drop otherwise. low transmission priority, p1 12.5 mbps apps: emails, file backups. latency: < 16 ms desired, but not critical. drop: no drop if p1 not oversubscribed. apps: casual web browsing. latency: < 16 ms desired, but not critical. drop: no drop if p1 not oversubscribed; first to drop otherwise. total 100 mbps table 3 - two-dimensional world traffic ZL50417 data sheet 27 zarlink semiconductor inc. best-effort (p0) traffic forms a fourth class that only receives bandwidth when none of the other classes have any traffic to offer. it is also possible to add a fourth class that has st rict priority over the other three; if this class has even one frame to transmit, then it goes first. in the ZL50417, each 10/100 mbps port will support four total classes, and each 1000 mbps port will support eight classes. we will discuss the various mode s of scheduling these classes in the next section. in addition, each transmission class has two subclasses, high-drop and low-drop. well-behaved users should rarely lose packets. but poorly behaved users ? users who send fr ames at too high a rate ? will encounter frame loss, and the first to be discarded will be high-drop. of course, if th is is insufficient to resolve the congestion, eventually some low-drop frames are dropped, and then all frames in the worst case. table 3 shows that different types of applications may be pl aced in different boxes in the traffic table. for example, casual web browsing fits into the category of high-loss, high-latency-tolerant traffic, whereas voip fits into the category of low-loss, low-latency traffic. 7.2 four qos configurations there are four basic pieces to qos scheduling in the zl50 417: strict priority (sp) , delay bound, weighted fair queuing (wfq), and best effort (be). using these four pieces , there are four different mo des of operation, as shown in the tables below. for 10/100 mbps ports, the following registers select these modes: qosc40 [7:6] and qosc48 [7:6 ] select these modes for the first and second gigabit ports, respectively. the default configuration for a 10/100 mbps port is three delay-bounded queues and one best-effort queue. the delay bounds per class are 0.8 ms for p3, 3.2 ms for p2, and 12.8 ms for p1. for a 1 gbps port, we have a default of six delay-bounded queues and two best-effort queues. the delay bounds for a 1 gbps port are 0.16 ms for p7 and p6, 0.32 ms for p5, 0.64 ms for p4, 1.28 ms for p3, and 2.56 ms for p2. best effort traffic is only served when qosc24 [7:6]_credit_c00 qosc28 [7:6]_credit_c10 qosc32 [7:6]_credit_c20 qosc36 [7:6]_credit_c30 p3 p2 p1 p0 op1 (default) delay bound be op2 sp delay bound be op3 sp wfq op4 wfq table 4 - four qos configurations for a 10/100 mbps port p7 p6 p5 p4 p3 p2 p1 p0 op1 (default) delay bound be op2 sp delay bound be op3 sp wfq op4 wfq table 5 - four qos configurations for a gigabit port ZL50417 data sheet 28 zarlink semiconductor inc. there is no delay-bounded traffic to be served. for a 1 gb ps port, where there are two best-effort queues, p1 has strict priority over p0. we have a second configuration for a 10/100 mbps port in which there is one strict priority queue, two delay bounded queues, and one best effort queue. the delay bounds per class are 3.2 ms for p2 and 12.8 ms for p1. if the user is to choose this conf iguration, it is important t hat p3 (sp) traffic be either policed or implicitly bounded (e.g. if the incoming p3 traffic is very light and predictably patterned). strict priority traf fic, if not admission-controlled at a prior stage to the ZL50417, can have an adverse effe ct on all other classes? performance. for a 1 gbps port, p7 and p6 are both sp classes, and p7 has strict priority over p6. in this case, the delay bounds per class are 0.32 ms for p5, 0.64 ms for p4, 1.28 ms for p3, and 2.56 ms for p2. the third configuration for a 10/100 mbps port contains one strict priority queue and three queues receiving a bandwidth partition via wfq. as in the second configuration, strict priority traffic needs to be carefull y controlled. in the fourth configuration, all queues are served using a wfq service discipline. 7.3 delay bound in the absence of a sophisticated qos server and signaling protocol, the ZL50417 may not know the mix of incoming traffic ahead of time. to cope with this uncertainty, our delay assurance algorithm dynamically adjusts its scheduling and dropping criteria, guided by the queue occupancies and the due dates of their head-of-line (hol) frames. as a result, we assure latency bounds for all admitt ed frames with high confidence, even in the presence of system-wide congestion. our algorithm identifies misbeh aving classes and intelligen tly discards frames at no detriment to well-behaved classes. our algorithm also di fferentiates between high-drop and low-drop traffic with a weighted random early drop (wred) approach. random early dropping prevents congestion by randomly dropping a percentage of high-drop frames even before the chip?s buffers are completely full, while still largely sparing low- drop frames. this allows high-drop frames to be discarded early, as a sacrifice for future low-drop frames. finally, the delay bound algorithm also achieves bandwidth partitioning among classes. 7.4 strict priority and best effort when strict priority is part of the scheduling algorithm, if a queue has even one frame to transmit, it goes first. two of our four qos configurations include st rict priority queues. the goal is for stri ct priority classes to be used for ietf expedited forwarding (ef), where performance guarantees ar e required. as we have indicated, it is important that strict priority traffic be either policed or implicitly bounded, so as to keep from harming other traffic classes. when best effort is part of the scheduling algorithm, a queue only receives bandwidth when none of the other classes have any traffic to offer. two of our four qos configurations in clude best effort queues. the goal is for best effort classes to be used for non-essential traffic, becaus e we provide no assurances about best effort performance. however, in a typical network setting, much best effort traffic will indeed be transm itted, and with an adequate degree of expediency. because we do not provide any delay assurances for best effort traffic, we do not enforce latency by dropping best effort traffic. furthermore, because we assume that strict priority traffic is carefully controlled before entering the ZL50417, we do not enforce a fair bandwidth partition by dr opping strict priority traffic. to summarize, dropping to enforce bandwidth or delay does not apply to strict priority or best effort queues. we only drop frames from best effort and strict priority queues when global buffer resources become scarce. ZL50417 data sheet 29 zarlink semiconductor inc. 7.5 weighted fair queuing in some environments ? for example, in an environment in which delay assurances are not required, but precise bandwidth partitioning on small time scales is essential, wfq may be preferable to a delay-bounded scheduling discipline. the ZL50417 provides the user with a wfq optio n with the understanding that delay assurances can not be provided if the incoming traffic pattern is uncontrolled. the user sets four wfq ?weights? (eight for gigabit ports) such that all weights are whole numbers and sum to 64. this provides per-class bandwidth partitioning with error within 2%. in wfq mode, though we do not assure frame latency, the ZL50417 still retains a set of dropping rules that helps to prevent congestion and trigger higher le vel protocol end-to-end flow control. as before, when strict priority is combined with wfq, we do not have special dropping rules for the strict priority queues, because the input traffic pattern is assumed to be carefully controlled at a prior stage. however, we do indeed drop frames from sp queues for global buffer management purposes. in addition, queue p0 for a 10/100 port (and queues p0 and p1 for a gigabit port) are treated as best effort from a droppi ng perspective, though they still are assured a percentage of bandwidth from a wfq scheduling perspective. what this means is that these particular queues are only affected by dropping when the global buffer count becomes low. 7.6 shaper although traffic shaping is not a primary function of t he ZL50417, the chip does implement a shaper for expedited forwarding (ef). our goal in shaping is to control the peak and average rate of traffic exiting the ZL50417. shaping is limited to the two gigabit ports only, and only to class p6 (the second highest priority). this means that class p6 will be the class used for ef traffic. if shaping is enabled for p6, then p6 traffic must be scheduled using strict priority. with reference to table 8, only the middle two qos configurations may be used. peak rate is set using a programmable whole number, no grea ter than 64. for example, if the setting is 32, then the peak rate for shaped traffic is 32/64 * 1000 mbps = 500 mbps. average rate is also a programmable whole number, no greater than 64, and no greater than the peak rate. for example, if the setting is 16, then the average rate for shaped traffic is 16/64 * 1000 mbps = 250 mbps. as a cons equence of the above settings in our example, shaped traffic will exit the ZL50417 at a rate always less than 500 mbps, and averaging no greater than 250 mbps. see programming qos register application note for more information. also, when shaping is enabled, it is possible for a p6 queue to explode in length if fed by a greedy source. the reason is that a shaper is by definition not work-conserving; that is, it may hold back from sending a packet even if the line is idle. though we do have global resource management, we do nothing to prevent this situation locally. we assume sp traffic is policed at a prior stage to the ZL50417. 7.7 wred drop threshold management support to avoid congestion, the weighted random early detection (wred) logic drops packets according to specified parameters. the following table summarizes the behavior of the wred logic. figure 11 - summary of the behaviour of the wred logic in kb (kilobytes) p3 p2 p1 high drop low drop level 1 n 120 p3 akb p2 bkb p1 ckb x% 0% level 2 n 140 y% z% level 3 n 160 100% 100% ZL50417 data sheet 30 zarlink semiconductor inc. px is the total byte count, in the priority queue x. the wred logic has three drop levels, depending on the value of n, which is based on the number of bytes in the priori ty queues. if delay bound scheduling is used, n equals p3*16+p2*4+p1. if using wfq scheduling, n equals p3+p2+p1. each drop level from one to three has defined high-drop and low-drop percentages, which indicate the mi nimum and maximum percentages of the data that can be discarded. the x, y z percent can be programmed by the register rdrc0, rdrc1. in level 3, all packets are dropped if the bytes in each priority queue exceed the thre shold. parameters a, b, c are the byte count thresholds for each priority queue. they can be programmed by the qo s control register (refer to the register group 5). see programming qos registers applicat ion note for more information. 7.8 buffer management because the number of fdb slots is a scarce resource, and because we want to ensure that one misbehaving source port or class cannot harm the performance of a well-behaved source port or class, we introduce the concept of buffer management into the ZL50417. our buffer management scheme is designed to divide the total buffer space into numerous reserved regions and one shared pool, as shown in figure 12 on page 31. as shown in the figure, the fdb pool is divided into se veral parts. a reserved region for temporary frames stores frames prior to receiving a switch response. such a temporary region is necessary, because when the frame first enters the ZL50417, its destination port and class are as ye t unknown, and so the decision to drop or not needs to be temporarily postponed. this ensures that every frame can be received first before subjecting them to the frame drop discipline after classifying. six reserved sections, one for each of the first six priority classes, ensure a programmable number of fdb slots per class. the lowest two classe s do not receive any buffer reservation. fu rthermore, even for 10/100 mbps ports, a frame is stored in the region of the fdb corresponding to it s class. as we have indicate d, the eight classes use only four transmission scheduling queues for 10/100 mbps ports, but as far as buffer usage is concerned, there are still eight distinguishable classes. another segment of the fdb reserves space for each of the 18 ports. two parameters can be set, one for the source port reservation for 10/100 mbps ports, and one for the source port reservatio n for 1 gbps ports. these 18 reserved regions make sure that no well-behaved source po rt can be blocked by another misbehaving source port. in addition, there is a shared pool, whic h can store any type of frame. the fr ame engine allocates the frames first in the six priority sections. when the priority section is full or the packet has priority 1 or 0, the frame is allocated in the shared poll. once the shared poll is full the frames are allocated in the section reserved for the source port. the following registers define the size of each section of the frame data buffer: pr100- port reservation for 10/100 ports prg- port reservation for giga ports sfcb- share fcb size c2rs- class 2 reserve size c3rs- class 3 reserve size c4rs- class 4 reserve size c5rs- class 5 reserve size c6rs- class 6 reserve size c7rs- class 7 reserve size ZL50417 data sheet 31 zarlink semiconductor inc. figure 12 - buffer partition scheme used to implement buffer management 7.8.1 dropping when buffers are scarce summarizing the two examples of local dropping discussed earlier in this chapter: if a queue is a delay-bounded queue, we have a multilev el wred drop scheme, designed to control delay and partition bandwidth in case of congestion. if a queue is a wfq-scheduled queue, we have a multilevel wred drop scheme, designed to prevent congestion. in addition to these reasons for dropping, we also drop frames when global buffer space becomes scarce. the function of buffer management is to make sure that such dropping causes as little blocking as possible. 7.9 ZL50417 flow control basics because frame loss is unacceptable for some applications, the ZL50417 provides a flow control option. when flow control is enabled, scarcity of buffer space in the switch may trigger a flow control signal; this signal tells a source port that is sending a packet to this switch, to temporarily hold off. while flow control offers the clear benefit of no packet lo ss, it also introduces a problem for quality of service. when a source port receives an ethernet flow control signal, a ll microflows originating at that port, well-behaved or not, are halted. a single packet destined for a congested output can block other packets destined for uncongested outputs. the resulting head-of-line blocking phenomenon means that quality of service cannot be assured with high confidence when flow control is enabled. in the ZL50417, each source port can independently ha ve flow control enabled or disabled. for flow control enabled ports, by default all frames are treated as lowest priority during tran smission scheduling. this is done so that those frames are not exposed to the wred dropping scheme. frames from flow control enabled ports feed to only one queue at the destination, the queue of lowest priori ty. what this means is that if flow control is enabled for a given source port, then we can guarantee that no packets originating from that port will be lost, but at the possible shared pool s per-source reservations (24 10/100 m, cpu) temporary reservation per-class reservation ZL50417 data sheet 32 zarlink semiconductor inc. expense of minimum bandwidth or maximum delay assura nces. in addition, these ?downgraded? frames may only use the shared pool or the per-source reserved pool in th e fdb; frames from flow control enabled sources may not use reserved fdb slots for th e highest six classes (p2-p7). the ZL50417 does provide a system-wide option of permitt ing normal qos sched uling (and buffer use) for frames originating from flow control enabled ports. when this pr ogrammable option is active, it is possible that some packets may be dropped, even though flow control is on. the reason is that intelligent packet dropping is a major component of the ZL50417?s approach to ensuring bounded delay and minimum bandwidth for high priority flows. 7.9.1 unicast flow control for unicast frames, flow control is triggered by source po rt resource availability. recall that the ZL50417?s buffer management scheme allocates a reserved number of fdb sl ots for each source port. if a programmed number of a source port?s reserved fdb slots have been used, then flow control xoff is triggered. xon is triggered when a port is currently being flow contro lled, and all of that port?s reserved fdb slots have been released. note that the ZL50417?s per-source-port fdb reservations a ssure that a source port that sends a single frame to a congested destination will not be flow controlled. 7.9.2 multicast flow control in unmanaged mode, flow cont rol for multicast frames is triggered by a global buffer co unter. when the system exceeds a programmable threshol d of multicast packets, xoff is triggered. xon is triggered wh en the system returns below this threshold. in addition, each source port has a 18-bit port map recording which port or ports of the multicast frame?s fanout were congested at the time xoff was triggered. all ports are continuously monitored for congestion, and a port is identified as uncongested when its queue occupancy falls below a fixed threshold. when all those ports that were originally marked as congested in the port map have be come uncongested, then xon is triggered, and the 18-bit vector is reset to zero. 7.10 mapping to ietf diffserv classes the mapping between priority classes discussed in this chapter and elsewhere is shown below. table 6 - mapping between ZL50417 and ietf diffserv classes for gigabit ports as the table illustrates, p7 is used solely for netw ork management (nm) frames. p6 is used for expedited forwarding service (ef). classe s p2 through p5 correspond to an assured forwarding (af) group of size 4. finally, p0 and p1 are two best effort (be) classes. zl504xx p7 p6 p5 p4 p3 p2 p1 p0 ietf nm ef af0 af1 af2 af3 be0 be1 ZL50417 data sheet 33 zarlink semiconductor inc. for 10/100 mbps ports, the classes of table 7 are merged in pairs?one class corresponding to nm+ef, two af classes, and a single be class. features of the ZL50417 that correspond to the requirements of their associated ietf classes are summarized in the table below. 8.0 port trunking 8.1 features and restrictions a port group (i.e., trunk) can include up to 4 physical port s, but when using stack all of the ports in a group must be in the same ZL50417. the two gigabit ports may also be trunked together. there ar e three trunk groups total, including the option to trunk gigabit ports. load distribution among the ports in a trunk for unicast is performed using hashing based on source mac address and destination mac address. three other options incl ude source mac address only, destination mac address only, and source port (in bidirectional ring mode only). load distribution for multicast is performed similarly. the ZL50417 also provides a safe fail-over mode for port trunking automatically. if one of the ports in the trunking group goes down, the ZL50417 will automatically redistribute the traffic over to the remaining ports in the trunk. zl504xx p3 p2 p1 p0 ietf nm+ef af0 af1 be0 table 7 - mapping between ZL50417 and ietf diffserv classes for 10/100 ports network management (nm) and expedited forwarding (ef) global buffer reservation for nm and ef shaper for ef traffic on 1 gbps ports option of strict priority scheduling no dropping if admission controlled assured forwarding (af) four af classes for 1 gbps ports programmable bandwidth partition, with option of wfq service option of delay-bounded service keeps delay under fixed levels even if not admission- controlled random early discard, with programmable levels global buffer reservation for each af class best effort (be) two be classes for 1 gbps ports service only when other queues are idle means that qos not adversely affected random early discard, with programmable levels traffic from flow control enabled ports automatically classified as be table 8 - ZL50417 features enabling ietf diffserv standards ZL50417 data sheet 34 zarlink semiconductor inc. 8.2 unicast packet forwarding the search engine finds the destination mct entry, and if the status field says that the destination port found belongs to a trunk, then the group number is retrieved inst ead of the port number. in addition, if the source address belongs to a trunk, then the source port? s trunk membership re gister is checked. a hash key, based on some combination of the source and destination mac addresses for the current packet, selects the appropriate forwarding port, as specified in the trunk_hash registers. 8.3 multicast packet forwarding for multicast packet forwarding, the de vice must determine the proper set of ports from which to transmit the packet based on the vlan index and hash key. two functions are required in order to distribute multic ast packets to the appropriate destination ports in a port trunking environment. determining one forwarding port per group. preventing the multicast packet from looping back to the source trunk. the search engine needs to prevent a multicast packet from sending to a port that is in the same trunk group with the source port. this is because, when we select the pr imary forwarding port for each group, we do not take the source port into account. to prevent this, we simply apply one additional filter, so as to block that forwarding port for this multicast packet. 8.4 trunking in this mode, 3 trunk groups are supported. groups 0 and 1 can trunk up to 4 10/100 ports. group 2 can trunk 2 gigabit ports. the supported combinations are shown in the following table. the trunks are individually enabled/disabled by controlling pin trunk 0, 1, 2. group 0 port 0 port 1 port 2 port 3 d d d d d d d d d table 9 - select via trunk0_mode register group 1 port 4 port 5 port 6 port 7 d d d d d d table 10 - select via trunk1_mode register group 2 port 25 (giga 0) port 26 (giga 1) d d table 11 - individually enabled/disabled ZL50417 data sheet 35 zarlink semiconductor inc. 9.0 port mirroring 9.1 port mirroring features the received or transmitted data of any 10/100 port in the ZL50417 chip can be ?mirrored? to any other port. we support two such mirrored source-destination pairs. a mirror port can not also serve as a data port. 9.2 setting registers for port mirroring mirror1_src: sets the source port for th e first port mirroring pair. bits [4:0] select the source port to be mirrored. an illegal port number is used to disable mirroring (which is the default setting). bit [5] is used to select between ingress (rx) or egress (tx) data. mirror1_dest: sets the destination port for the first port mi rroring pair. bits [4:0] sele ct the destination port to be mirrored. mirror2_src: sets the source port for the second port mi rroring pair. bits [4:0] sele ct the source port to be mirrored. an illegal port number is used to disable mirroring (which is the default setting). bit [5] is used to select between ingress (rx) or egress (tx) data. mirror2_dest: sets the destination port for the second port mirroring pair. bits [4:0] select the destination port to be mirrored. the default is port 0. refer to port mirroring applicat ion notes for further information. ZL50417 data sheet 36 zarlink semiconductor inc. 10.0 tbi interface 10.1 tbi connection the tbi interface can be used for 1000 mbps fiber operation. in this mode, the ZL50417 is connected to the serdes as shown in figure 13. there are two tbi interfaces in the ZL50417 devices. to enable to tbi function, the corresponding txen and txer pins need to be boot strapped. see ball ? signal description for details. figure 13 - tbi connection ZL50417 serdes m25/26_txd[9:0] m25/26_txclk m25/26_rxclk m25/26_col m25/26_rxd[9:0] rbc0 rbc1 t[9:0] r[9:0] refclk ZL50417 data sheet 37 zarlink semiconductor inc. 11.0 gpsi (7ws) interface 11.1 gpsi connection the 10/100 rmii ethernet port can fu nction in gpsi (7ws) mode when the corresponding txen pin is strapped low with a 1 k pull down resistor. in this mode, the txd[0] , txd[1], rxd[0] and rxd[1] serve as tx data, tx clock, rx data and rx clock respectively. the link status and collision from the phy are multiplexed and shifted into the switch device through external glue logic. the duplex of the port can be controlled by programming the ecr register. the gpsi interface can be operated in port based vlan mode only. figure 14 - gpsi (7ws) mode connection diagram 5041x port 0 ethernet phy crs rxd rx_clk tx_clk txd txen txd[1] txd[0] txen rxd[1] rxd[0] crs_dv port 15 ethernet phy link serializer (cpld) link0 link1 link2 link15 scan_link scan_clk collision serializer (cpld) col0 col1 col2 col15 scan_col ZL50417 data sheet 38 zarlink semiconductor inc. 11.2 scan link and scan col interface an external cpld logic is required to take the link si gnals and collision signals from the gpsi phys and shift them into the switch device. the switch device will drive out a signature to indicate the start of the sequence. after that, the cpld should shift in the link and collision status of the phys as shown in the figure. the extra link status indicates the polarity of the link signal. one indicates the polarity of the link signal is active high. figure 15 - scan link and scan collison status diagram scan_clk scan_link/ scan_col drived by zl5041x drived by cpld 25 cycles for link/ 24 cycles for col total 32 cycles period ZL50417 data sheet 39 zarlink semiconductor inc. 12.0 led interface 12.1 led interface introduction a serial output channel provides port status information fr om the ZL50417 chips. it requires three additional pins. led_clk at 12.5 mhz led_syn a sync pulse that defines the boundary between status frames led_data a continuous serial stream of data for all status leds that repeats once every frame time a non-serial interface is also allowed, but in this ca se, only the gigabit ports will have status leds. a low cost external device (44 pin pal) is used to decode the serial data and to drive an led array for display. this device can be customiz ed for different needs. 12.2 port status in the ZL50417, each port has 8 status indicators, each represented by a single bit. the 8 led status indicators are: - bit 0: flow control - bit 1:transmit data - bit 2: receive data - bit 3: activity (where activity includes either transmission or reception of data) - bit 4: link up - bit 5: speed ( 1= 100 mb/s; 0 = 10 mb/s) - bit 6: full-duplex - bit 7: collision eight clocks are required to cycle through the eight status bits for each port. when the led_syn pulse is asserted, the led inte rface will present 256 led cl ock cycles with the clock cycles providing information for the following ports. - port 0 (10/100): cycles #0 to cycle #7 - port 1 (10/100): cycles#8 to cycle #15 - port 2 (10/100): cycle #16 to cycle #23 -... - port 14 (10/100): cycle #112 to cycle #119 - port 15 (10/100): cycl e #120 to cycle #127 - port 25 (gigabit 1): cycle #192 to cycle #199 - port 26 (gigabit 2): cycle #200 to cycle #207 - byte 26 (addi tional status): cycle #208 to cycle #215 - byte 27 (addi tional status): cycle #216 to cycle #223 cycles #224 to 256 present data with a value of zero. ZL50417 data sheet 40 zarlink semiconductor inc. the first two bits of byte 26 provides the speed information for the gigabit ports while the remainder of byte 26 and byte 27 provides bist status - 26[0]: g0 port (1 = port 24 is operating at gigabit speed; 0 = speed is either 10 or 100 mb/s depending on speed bit of port 24) - 26[1]: g1 port (1 = port 25 is operating at gigabit speed; 0 = speed is either 10 or 100 mb/s depending on speed bit of port 25) - 26[2]: initialization done - 26[3]: initialization start - 26[4]: checksum ok - 26[5]: link_init_complete - 26[6]: bist_fail - 26[7]: ram_error - 27[0]: bist_in_process - 27[1]: bist_done 12.3 led interface timing diagram the signal from the ZL50417 to the led decoder is shown in figure 16. . figure 16 - timing diagram of led interface ZL50417 data sheet 41 zarlink semiconductor inc. 13.0 register definition 13.1 ZL50417 register description register description cpu addr (hex) r/w i2c addr (hex) default notes 0. ethernet port control regi sters substitute [n] with port number (0..f, 18-1a) ecr1p?n? port control register 1 for port n 0000 + 2 x n r/w 000- 01a 020 ecr2p?n? port control register 2 for port n 001 + 2 x n r/w 01b- 035 000 ggc extra giga bit control register 036 r/w na 000 1. vlan control registers substitute [n] with port number (0..f, 18-1a) avtcl vlan type code register low 100 r/w 036 000 avtch vlan type code register high 101 r/w 037 081 pvmap?n?_0 port ?n? configuration register 0 102 + 4n r/w 038-052 0ff pvmap?n?_1 port ?n? configuration register 1 103 + 4n r/w 053- 06d 0ff pvmap?n?_3 port ?n? configuration register 3 105 + 4n r/w 089- 0a3 007 pvmode vlan operating mode 170 r/w 0a4 000 pvroute7-0 vlan router group enable 171-178 r/w na 000 2. trunk control registers trunk0_ mode trunk group 0 mode 203 r/w 0a5 003 3. cpu port configuration rqss receive queue status 324 ro na n/a tx_age transmission queue aging time 325 r/w 0a7 008 4. search engine configurations agetime_low mac address aging time low 400 r/w 0a8 2m:05c/ 4m:02e agetime_ high mac address ag ing time high 401 r/w 0a9 000 se_opmode search engine operating mode 403 r/w na 000 5. buffer control and qos control fcbat fcb aging timer 500 r/w 0aa 0ff qosc qos control 501 r/w 0ab 000 ZL50417 data sheet 42 zarlink semiconductor inc. fcr flooding control register 502 r/w 0ac 008 avpml vlan priority map low 503 r/w 0ad 000 avpmm vlan priority map middle 504 r/w 0ae 000 avpmh vlan priority map high 505 r/w 0af 000 tospml tos priority map low 506 r/w 0b0 000 tospmm tos priority map middle 507 r/w 0b1 000 tospmh tos priority map high 508 r/w 0b2 000 avdm vlan discard map 509 r/w 0b3 000 tosdml tos discard map 50a r/w 0b4 000 bmrc broadcast/multicast rate control 50b r/w 0b5 000 ucc unicast congestion control 50c r/w 0b6 2m:008/ 4m:010 mcc multicast congestion control 50d r/w 0b7 050 pr100 port reservation for 10/100 ports 50e r/w 0b8 2m:024/ 4m:036 prg port reservation for giga ports 50f r/w 0b9 2m:035/ 4m:058 sfcb share fcb size 510 r/w 0ba 2m:014/ 4m:064 c2rs class 2 reserve size 511 r/w 0bb 000 c3rs class 3 reserve size 512 r/w 0bc 000 c4rs class 4 reserve size 513 r/w 0bd 000 c5rs class 5 reserve size 514 r/w 0be 000 c6rs class 6 reserve size 515 r/w 0bf 000 c7rs class 7 reserve size 516 r/w 0c0 000 qosc?n? qos control (n=0 - 5) 517- 51c r/w 0c1- 0c6 000 qos control (n=6 - 11) 51d- 522 r/w na 000 qos control (n=12 - 23) 523- 52e r/w 0c7- 0d2 000 qos control (n=24 - 59) 52f- 552 r/w na 000 rdrc0 wred drop rate control 0 553 r/w 0fb 08f register description cpu addr (hex) r/w i2c addr (hex) default notes ZL50417 data sheet 43 zarlink semiconductor inc. rdrc1 wred drop rate control 1 554 r/w 0fc 088 user_ port?n?_low user define logical port ?n? low (n=0-7) 580 + 2n r/w 0d6- 0dd 000 user_ port?n?_high user define logical port ?n? high 581 + 2n r/w 0de- 0e5 000 user_ port1:0_ priority user define logic port 1 and 0 priority 590 r/w 0e6 000 user_ port3:2_ priority user define logic port 3 and 2 priority 591 r/w 0e7 000 user_ port5:4_ priority user define logic port 5 and 4 priority 592 r/w 0e8 000 user_ port7:6_pri ority user define logic port 7 and 6 priority 593 r/w 0e9 000 user_port_ enable user define logic port enable 594 r/w 0ea 000 wlpp10 well known logic port priority for 1 and 0 595 r/w 0eb 000 wlpp32 well known logic port priority for 3 and 2 596 r/w 0ec 000 wlpp54 well known logic port priority for 5 and 4 597 r/w 0ed 000 wlpp76 well-known logic po rt priority for 7 & 6 598 r/w 0ee 000 wlpe well known logic port enable 599 r/w 0ef 000 rlowl user define range low bit7:0 59a r/w 0f4 000 rlowh user define range low bit 15:8 59b r/w 0f5 000 rhighl user define range high bit 7:0 59c r/w 0d3 000 rhighh user define range high bit 15:8 59d r/w 0d4 000 rpriority user define ra nge priority 59e r/w 0d5 000 6. misc configuration registers mii_op0 mii register option 0 600 r/w 0f0 000 mii_op1 mii register option 1 601 r/w 0f1 000 register description cpu addr (hex) r/w i2c addr (hex) default notes ZL50417 data sheet 44 zarlink semiconductor inc. fen feature registers 602 r/w 0f2 010 miic0 mii command register 0 603 r/w n/a 000 miic1 mii command register 1 604 r/w n/a 000 miic2 mii command register 2 605 r/w n/a 000 miic3 mii command register 3 606 r/w n/a 000 miid0 mii data register 0 607 ro n/a n/a miid1 mii data register 1 608 ro n/a n/a led led control register 609 r/w 0f3 000 sum eeprom checksum register 60b r/w 0ff 000 7. port mirroring controls mirror1_src port mirror 1 source port 700 r/w n/a 07f mirror1_ dest port mirror 1 de stination port 701 r/w n/a 017 mirror2_src port mirror 2 source port 702 r/w n/a 0ff mirror2_ dest port mirror 2 de stination port 703 r/w n/a 000 2 gcr global control register f00 r/w n/a 000 dcr device status and signature register f01 ro n/a n/a dcr1 giga port status f02 ro n/a n/a dpst device port status register f03 r/w n/a 000 dtst data read back register f04 ro n/a n/a da da register fff ro n/a da register description cpu addr (hex) r/w i2c addr (hex) default notes ZL50417 data sheet 45 zarlink semiconductor inc. 13.2 (group 0 address) mac ports group 13.2.1 ecr1pn: port n control register i2c address 000 - 01a; cpu address:0000+2xn (n = port number) accessed by serial in terface and i2c (r/w) 765 4321 0 sp state a-fc port mode bit [0] ? 1 - flow control off ? 0 - flow control on ? when flow control on: ? in half duplex mode, the mac transmitter applies back pressure for flow control. ? in full duplex mode, the mac transmitter sends flow control frames when necessary. the mac receiver interprets and processes incoming flow control frames. the flow control frame received counter is incremented whenever a flow control is received. ? when flow control off: ? in half duplex mode, the mac transmitter does not assert flow control by sending flow control frames or jamming collision. ? in full duplex mode, the mac transmitter does not se nd flow control frames. the mac receiver does not interpret or process the flow control frames. the flow control frame received counter is not incremented. bit [1] ? 1 - half duplex - only in 10/100 mode ? 0 - full duplex bit [2] ? 1 - 10 mbps ? 0 - 100 mbps bit [4:3] ? 00 ? automatic enable auto neg. - this enables hardware state machine for auto-negotiation. ? 01 - limited disable auto neg. this disables hardware for speed auto- negotiation. hardware po ll mii for link status. ? 10 - link down. force link down (disable the port). ? 11 - link up. the configuration in ecr1 [2:0] is used for (speed/half duplex/full duplex/flow control) setup. bit [5] ? asymmetric flow control enable. ? 0 ? disable asymmetric flow control ? 01 ? enable asymme tric flow control ? when this bit is set, and flow control is on (bit [0] = 0), don?t send out a flow control frame. but mac receiver interprets and processes flow control frames. ZL50417 data sheet 46 zarlink semiconductor inc. 13.2.2 ecr2pn: port n control register i2c address: 01b-035; cpu address:0001+2xn (n = port number) accessed by serial in terface and i2c (r/w) bit [7:6] ? ss - spanning tree state (802.1d spanning tree protocol) default is 11 . ? 00 ? blocking: frame is dropped ? 01 - listening: frame is dropped ? 10 - learning: frame is dropped. source mac address is learned. ? 11 - forwarding: frame is forwarded. source mac address is learned. 7654 3 210 security en qos sel reserve disl ftf futf bit [0]: ? filter untagged frame ( default 0 ) ? 0: disable ? 1: all untagged frames from this port are discarded or follow security option when security is enable bit [1]: ? filter tag frame ( default 0 ) ? 0: disable ? 1: all tagged frames from this port are discarded or follow secu rity option when security is enable bit [2]: ? learning disable (default 0) ? 1 learning is disabled on this port ? 0 learning is enabled on this port bit [3]: ? must be ?1? bit [5:4:] ? qos mode selection (default 00) ? determines which of the 4 sets of qos settings is used for 10/100 ports. ? note that there are 4 sets of per-queue byte thresholds, and 4 sets of wfq ratios programmed. these bits select among the 4 choices for each 10/100 port. refer to qos application note. ? 00: select class byte limit se t 0 and classes wfq credit set 0 ? 01: select class byte limit se t 1 and classes wfq credit set 1 ? 10: select class byte limit se t 2 and classes wfq credit set 2 ? 11: select class byte limit se t 3 and classes wfq credit set 3 bit [7:6] ? security enable (default 00). the ZL50417 checks the incoming data for one of the following conditions: ? if the source mac address of the incoming packet is in the mac table and is defined as secure address but the ingress port is not the same as the port associated with the mac address in the mac table. ZL50417 data sheet 47 zarlink semiconductor inc. 13.2.3 ggcontrol ? extra giga port control cpu address:h036 accessed by cpu and serial interface (r/w) ? a mac address is defined as secure when its entry at mac table has static status and bit 0 is set to 1. mac addr ess bit 0 (the firs t bit transmitted) indicates whether the address is unicast or multicast. as source addresses are always unicast bit 0 is not used (always 0). ZL50417 uses this bit to define secure mac addresses. ? if the port is set as learning disable and the source mac address of the incoming packet is not defined in the mac address table. ? if the port is configured to filter untagged frames and an untagged frame arrives or if the port is configured to filter tagged frames and a tagged frame arrives. ? if the port is configured to filter untagged frames and an untagged frame arrives or if the port is configured to filter tagged frames and a tagged frame arrives. ? if one of these three conditions occurs, the packet will be handled according to one of the following specified options: ?cpu installed - 00 ? disable port security - 01 ? discard violating packets - 10 ? send packet to cpu and destination port - 11 ? send packet to cpu only 765 4 321 0 df miib rsta df miia rsta bit [0]: ? reset giga port a - 0: normal operation (default) - 1: reset gigabit port a. normally used when a new phy is connected (hot swap). bit [1]: ? giga port a use mii interface (10/100 m) - 0: gigabit port operations at 1000 mode (default) - 1: gigabit port operations at 10/100 mode bit [2]: ? reserved - must be zero bit [3]: ? giga port a direct flow control (mac to mac connection). the ZL50417 suppor ts direct flow control mechanism; the flow control frame is therefore not sent through the gigabit port data path. - 0: direct flow control disabled (default) - 1: direct flow control enabled ZL50417 data sheet 48 zarlink semiconductor inc. 13.3 (group 1 address) vlan group 13.3.1 avtcl ? vlan type code register low i2c address 036; cpu address:h100 accessed serial interface and i2c (r/w) 13.3.2 avtch ? vlan type code register high i2c address 037; cpu address:h101 accessed by serial in terface and i2c (r/w) 13.3.3 pvmap00_0 ? port 00 configuration register 0 i2c address 038, cpu address:h102 accessed by serial in terface and i2c (r/w) in port based vlan mode this register indicates the legal egress ports. a ?1? on bit 7 means that the packet can be sent to port 7. a ?0? on bit 7 means that any packet destined to port 7 will be discarded . this register works with registers 1, 2 and 3 to form a 27 bit mask to all egress ports. bit [4]: ? reset giga port b - 0: normal operation (default) - 1: reset gigabit port b bit [5]: ? giga port b use mii interface (10/100 m) - 0: gigabit port operates at 1000 mode (default) - 1: gigabit port operates at 10/100 mode bit [6]: ? reserved - must be zero bit [7]: ? giga port b direct flow control (mac to mac connection). zl 50417 suppor ts direct flow control mechanism; the flow control frame is therefore not sent through the gigabit port data path. - 0: direct flow control disabled (default) - 1: direct flow control enabled bit [7:0]: vlantype_low: lower 8 bits of the vlan type code (default 00) bit [7:0]: vlantype_high: upper 8 bits of the vlan type code (default is 81) bit [7:0]: vlan mask for ports 7 to 0 (default ff) ZL50417 data sheet 49 zarlink semiconductor inc. 13.3.4 pvmap00_1 ? port 00 configuration register 1 i2c address h53, cpu address:h103 accessed by serial in terface and i2c (r/w) in port based vlan mode 13.3.5 pvmap00_3 ? port 00 configuration register 3 i2c address h89, cpu address:h105) accessed by serial in terface and i2c (r/w) in port based vlan mode bit [7:0]: vlan mask for ports 15 to 8 (default is ff) 765 32 0 fp en drop default tx priority vlan mask bit [2:0]: vlan mask for ports 26 to 24 (default 7). bit [5:3]: default transmit pr iority. used when bit [7]=1 (default 0) ? 000 transmit priority level 0 (lowest) ? 001 transmit priority level 1 ? 010 transmit priority level 2 ? 011 transmit priority level 3 ? 100 transmit priority level 4 ? 101 transmit priority level 5 ? 110 transmit priority level 6 ? 111 transmit priority level 7 (highest) bit [6]: default di scard priority. used when bit [7]=1 (default 0) ? 0 - discard priority level 0 (lowest) ? 1 - discard priority level 1(highest) bit [7]: enable fix priority ( default 0 ) ? 0 disable fix priority. all frames are analyzed. transmit priority and discard priority are based on vlan tag, tos or logical port. ? 1 transmit priority and discard priority are based on values programmed in bit [6:3] ZL50417 data sheet 50 zarlink semiconductor inc. 13.4 port configuration registers pvmap01_0,1,3 i2c address h39,54,8a; cpu address:h106,107,109 pvmap02_0,1,3 i2c address h3a,55,8b; cpu address:h10a, 10b, 10d pvmap03_0,1,3 i2c address h3b,56,8c; cpu address:h10e, 10f, 111 pvmap04_0,1,3 i2c address h3c,57,8d; cpu address:h112, 113, 115 pvmap05_0,1,3 i2c address h3d,58,8e; cpu address:h116, 117, 119 pvmap06_0,1,3 i2c address h3e,59,8f; cpu address:h11a, 11b, 11d pvmap07_0,1,3 i2c address h3f,5a,90; cpu address:h11e, 11f, 121 pvmap08_0,1,3 i2c address h40,5b,91; cpu address:h122, 123, 125 pvmap09_0,1,3 i2c address h41,5c,92; cpu address:h126, 127, 129 pvmap10_0,1,3 i2c address h42,5d,93; cpu address:h12a, 12b, 12d pvmap11_0,1,3 i2c address h43,5e,94; cpu address:h12e, 12f, 131 pvmap12_0,1,3 i2c address h44,5f,95; cpu address:h132, 133, 135 pvmap13_0,1,3 i2c address h45,60,96; cpu address:h136, 137, 139 pvmap14_0,1,3 i2c address h46,61,97; cpu address:h13a, h13b, 13d pvmap15_0,1,3 i2c address h47,62,98; cpu address:h13e, 13f, 141 pvmap25_0,1,3 i2c address h51,6c,a2; cpu address:h1 66, 167, 168, 169 (gigabit port 1) pvmap26_0,1,3 i2c address h52,6d,a3; cpu addre ss:h16a, 16b, 16d (gigabit port 2) 13.4.1 pvmode i2c address: h0a4, cpu address:h170 accessed by cpu, serial interface (r/w) 7 5 4 321 0 smo dl sl bit [0]: ? reserved -must be ?0? bit [1]: ? slow learning (default = 0) same function as se_op mode bit 7. either bit can enable the function; both need to be turned off to disable the feature. bit [2]: ? disable dropping of frames with destination mac addresses 0180c2000001 to 0180c200000f (default = 0) - 0: drop all frames in this range - 1: disable dropping of frames in this range ZL50417 data sheet 51 zarlink semiconductor inc. 13.5 (group 2 address) port trunking groups trunk group 0 - up to four 10/100 ports can be selected for trunk group 0. 13.5.1 trunk0_mode? trunk group 0 mode i2c address h0a5; cpu address:203 accessed by serial in terface and i2c (r/w) 13.5.2 trunk1_mode ? trunk group 1 mode i2c address h0a6; cpu address:20b accessed by serial in terface and i2c (r/w) bit [3]: ? reserved bit [4]: ? support mac address 0 (default = 0) - 0: mac address 0 is not learned. - 1: mac address 0 is learned. bit [7:5]: ? reserved 743210 hash select port select bit [1:0]: ? port selection in unmanaged mode. input pin trunk0 enable/disable trunk group 0 in unmanaged mode. - 00 reserved - 01 port 0 and 1 are used for trunk0 - 10 port 0,1 and 2 are used for trunk0 - 11 port 0,1,2 and 3 are used for trunk0 bit [3:2] ? hash select. the hash selected is valid for trunk 0, 1 and 2. (default 00) - 00 use source and destination mac address for hashing - 01 use source mac address for hashing - 10 use destination mac address for hashing - 11 use source destination mac address and ingress physical port number for hashing 7 210 port select ZL50417 data sheet 52 zarlink semiconductor inc. trunk group 2 13.5.3 trunk2_mode ? trunk group 2 mode (gigabit ports 1 and 2) cpu address:210 accessed by serial interface (r/w) 13.5.4 rqss ? receive queue status cpu address:h324 accessed by serial interface (ro) bit [5:0]: unit of 100 ms (default 8) disable transmission queue aging if value is zero. aging timer for all ports and queues. this register must be set to 0 fo r ?no packet loss flow control test?. bit [1:0]: ? port selection in unmanaged mode. input pin trunk1 enable/disable trunk group 1 in unmanaged mode. - 00 reserved - 01 port 4 and 5 are used for trunk1 - 10 reserved - 11 port 4, 5, 6 and 7 are used for trunk1 76 43 0 ring/trunk mode bit [3:0] ? reserved bit [6:4] ? 000 normal ? 001 trunk mode. enable trunk group for gigabit port 1 and 2 in managed mode. in unmanaged mode trunk 2 is enable/disable using input pin trunk2. ? 010 single ring with g1 ? 100 single ring with g2 ? 111 dual ring mode 76 5 0 tx queue agent ZL50417 data sheet 53 zarlink semiconductor inc. 13.6 (group 4 address) search engine group 13.6.1 agetime_low ? mac address aging time low i2c address h0a8; cpu address:h400 accessed by serial in terface and i2c (r/w) bit [7:0] low byte of the mac address aging timer mac address aging is enable/disable by boot strap tstout9 13.6.2 agetime_high ?mac address aging time high i2c address h0a9; cpu address h401 accessed by serial in terface and i2c (r/w) bit [7:0]: high byte of the mac address aging timer. the default setting provide 300 seconds aging time. aging time is based on the following equation: {agetime_time,agetime_low} x (# of mac entries in the memory x100 sec). number of mac entries = 32 k when 1 mb is used per bank. number of entries = 64 k when 2 mb is used per bank. 13.6.3 se_opmode ? search engine operation mode cpu address:h403 accessed by serial interface (r/w) {se_opmode} x(# of entries 100 u sec) 76 5 0 sl dms bit [5:0]: ? reserved bit [6]: ? disable mct speedup aging (default 0) - 1 ? disable speedup aging when mct resource is low. - 0 ? enable speedup aging when mct resource is low. bit [7]: ? slow learning (default 0) - 1? enable slow learning. learning is temporary disabled when search demand is high - 0 ? learning is performed independent of search demand ZL50417 data sheet 54 zarlink semiconductor inc. 13.7 (group 5 address) buffer control/qos group 13.7.1 fcbat ? fcb aging timer i2c address h0aa; cpu address:h500 13.7.2 qosc ? qos control i2c address h0ab; cpu address:h501 accessed by serial in terface and i2c (r/w) 13.7.3 fcr ? flooding control register i2c address h0ac; cpu address:h502 accessed by serial in terface and i2c (r/w) 70 fcbat bit [7:0]: ? fcb aging time. unit of 1 ms. (default ff) ? this is for buffer aging control. it is used to configure the buffer aging time. this function can be enabled/disabled through bootstrap pin. it is not suggested to use this function for normal operation. 76 5 43 10 tos-d tos-p vf1c l bit [0]: ? qos frame lost is ok. priority will be available for flow control enabled source only when this bit is set (default 0) bit [4]: ? per vlan multicast flow control (default 0) ?0 ? disable ?1 ? enable bit [5]: - reserved bit [6]: ? select tos bits for priority (default 0) ? 0 ? use tos [4:2] bits to map the transmit priority ? 1 ? use tos [7:5] bits to map the transmit priority bit [7]: ? select tos bits for drop priority (default 0) ? 0 ? use tos [4:2] bits to map the drop priority ? 1 ? use tos [7:5] bits to map the drop priority 76 43 0 tos timebase u2mr ZL50417 data sheet 55 zarlink semiconductor inc. 13.7.4 avpml ? vlan priority map i2c address h0ad; cpu address:h503 accessed by serial in terface and i2c (r/w) registers avpml, avpmm, and avpmh allow the eight vlan ta g priorities to ma p into eight intern al level transmit priorities. under the internal transmit priority, registers avpml, avpmm, and avpmh allow the eight vlan priorities to map into eight internal level transmit priori ties. under the internal transmit priority, seven is highest priority where as zero is the lowest. this feature allows the user the flexibility of redefining the vlan priority field. for example, programming a value of 7 into bit 2:0 of t he avpml register would map vlan priority 0 into internal transmit priority 7. the new priority is used inside the ZL50417. when the packet goes out it carries the original priority. bit [3:0]: ? u2mr: unicast to multicast rate. units in terms of ti me base defined in bits [6:4]. this is used to limit the amount of flooding traffic. the value in u2mr specifies how many packets are allowed to flood within the time specified by bit [6:4]. to disable th is function, prog ram u2mr to 0. (default = 8) bit [6:4]: time base: (default = 000) - 000 = 100 us - 001 = 200 us - 010 = 400 us -011 = 800us - 100 = 1.6 ms - 101 = 3.2 ms - 110 = 6.4 ms - 111 = 100 us, same as 000. bit [7]: select vlan tag or tos (ip packets) to be preferentially picked to map transmit priority and drop priority ( default = 0 ). - 0 ? select vlan tag priority field over tos - 1 ? select tos over vlan tag priority field 765 32 0 vp2 vp1 vp0 bit [2:0]: priority when the vl an tag priority field is 0 (default 0) bit [5:3]: priority when the vl an tag priority field is 1 ( default 0) bit [7:6]: priority when the vl an tag priority field is 2 (default 0) ZL50417 data sheet 56 zarlink semiconductor inc. 13.7.5 avpmm ? vlan priority map i2c address h0ae, cpu address:h504 accessed by serial in terface and i2c (r/w) map vlan priority into eigh t level transmit priorities: 13.7.6 avpmh ? vlan priority map i2c address h0af, cpu address:h505 accessed by serial in terface and i2c (r/w) map vlan priority into eigh t level transmit priorities: 13.7.7 tospml ? tos priority map i2c address h0b0, cpu address:h506 accessed by serial in terface and i2c (r/w) map tos field in ip packet into eight leve l transmit priorities 76 43 1 0 vp5 vp4 vp3 vp2 bit [0]: priority when the vl an tag priority field is 2 (default 0) bit [3:1]: priority when the vl an tag priority field is 3 (default 0) bit [6:4]: priority when the vl an tag priority field is 4 (default 0) bit [7]: priority when the vl an tag priority field is 5 (default 0) 754210 vp7 vp6 vp5 bit [1:0]: priority when the vl an tag priority field is 5 (default 0) bit [4:2]: priority when the vl an tag priority field is 6 (default 0) bit [7:5]: priority when the vl an tag priority field is 7 (default 0) 76 5 32 0 tp2 tp1 tp0 bit [2:0]: priority when the tos field is 0 (default 0) bit [5:3]: priority when the tos field is 1 (default 0) bit [7:6]: priority when the tos field is 2 (default 0) ZL50417 data sheet 57 zarlink semiconductor inc. 13.7.8 tospmm ? tos priority map i2c address h0b1, cpu address:h507 accessed by serial in terface and i2c (r/w) map tos field in ip packet into eight leve l transmit priorities 13.7.9 tospmh ? tos priority map i2c address h0b2, cpu address:h508 accessed by serial in terface and i2c (r/w) map tos field in ip pa cket into eight level transmit priorities: 13.7.10 avdm ? vlan discard map i2c address h0b3, cpu address:h509 accessed by serial in terface and i2c (r/w) map vlan priority into frame discard when low priority buffer usage is above threshold 76 43 10 tp5 tp4 tp3 tp2 bit [0]: priority when the tos field is 2 (default 0) bit [3:1]: priority when the tos field is 3 (default 0) bit [6:4]: priority when the tos field is 4 (default 0) bit [7]: priority when the tos field is 5 (default 0) 75420 tp7 tp6 tp5 bit [1:0]: priority when the tos field is 5 (default 0) bit [4:2]: priority when the tos field is 6 (default 0) bit [7:5]: priority when the tos field is 7 (default 0) 76543210 fdv7 fdv6 fdv5 fdv4 fdv3 fdv2 fdv1 fdv0 bit [0]: frame drop priority when vlan tag priority field is 0 (default 0) bit [1]: frame drop priority when vlan tag priority field is 1 (default 0) bit [2]: frame drop priority when vlan tag priority field is 2 (default 0) bit [3]: frame drop priority when vlan tag priority field is 3 (default 0) bit [4]: frame drop priority when vlan tag priority field is 4 (default 0) ZL50417 data sheet 58 zarlink semiconductor inc. 13.7.11 tosdml ? tos discard map i2c address h0b4, cpu address:h50a accessed by serial in terface and i2c (r/w) map tos into frame discard when low priority buffer usage is above threshold 13.7.12 bmrc - broadcast/multicast rate control i2c address h0b5, cpu address:h50b) accessed by serial in terface and i2c (r/w) this broadcast and multicast rate defines for each port, the number of packets allowed to be forwarded within a specified time. once the packet rate is reached, packets will be dropped. to turn off the rate limit, program the field to 0. time base is based on register fcr [6:4] bit [5]: frame drop priority when vlan tag priority field is 5 (default 0) bit [6]: frame drop priority when vlan tag priority field is 6 (default 0) bit [7]: frame drop priority when vlan tag priority field is 7 (default 0) 7 654321 0 fdt7 fdt6 fdt5 fdt4 fdt3 fdt2 fdt1 fdt0 bit [0]: frame drop priority when tos field is 0 (default 0) bit [1]: frame drop priority when tos field is 1 (default 0) bit [2]: frame drop priority when tos field is 2 (default 0) bit [3]: frame drop priority when tos field is 3 (default 0) bit [4]: frame drop priority when tos field is 4 (default 0) bit [5]: frame drop priority when tos field is 5 (default 0) bit [6]: frame drop priority when tos field is 6 (default 0) bit [7]: frame drop priority when tos field is 7 (default 0) 7430 broadcast rate multicast rate bit [3:0]: multicast rate control. number of multicast packets allowed within the time defined in bits 6 to 4 of the flooding control register (fcr). (default 0) . bit [7:4]: broadcast rate control. number of broadcast packets allowed within the time defined in bits 6 to 4 of the flooding control register (fcr). (default 0) ZL50417 data sheet 59 zarlink semiconductor inc. 13.7.13 ucc ? unicast congestion control i2c address h0b6, cpu address: 50c accessed by serial in terface and i2c (r/w) 13.7.14 mcc ? multicast congestion control i2c address h0b7, cpu address: 50d accessed by serial in terface and i2c (r/w) 13.7.15 pr100 ? port reservation for 10/100 ports i2c address h0b8, cpu address 50e accessed by serial in terface and i2c (r/w) 70 unicast congest threshold bit [7:0]: number of frame count. used for best effort dropping at b% when destination port?s best effort queue reaches ucc threshold and shared pool is all in use. granularity 1 frame. (default: h10 for 2 mb/bank or h08 for 1 mb/bank) 754 0 fc reaction period multicast congest threshold bit [4:0]: in multiples of two frames (granularity). used fo r triggering mc flow control when destination port?s multicast best effort queue reaches mcc threshold.(default 0x10) bit [7:5]: flow control reaction period (default 2) granularity 4 usec. 7430 buffer low threshold sp buffer reservation bit [3:0]: per source por t buffer reservation. define the space in the fdb reserved for each 10/100 port and cpu. expressed in multiples of 4 packets . for each packet 1536 bytes are reserved in the memory. bits [7:4]: expressed in multiples of 4 packets. threshold for dropping all best effort frames when destination port best efforts queues reaches ucc threshold, shared pool is all used and source port reservation is at or below the pr100 [7:4] level. also the threshold for initiating uc flow control. ?default: - h36 for 16+2 configuration with memory 2 mb/bank; - h24 for 16+2 configuration with 1 mb/bank; ZL50417 data sheet 60 zarlink semiconductor inc. 13.7.16 prg ? port reservation for giga ports i2c address h0b9, cpu address 50f accessed by serial in terface and i2c (r/w) 13.7.17 sfcb ? share fcb size i2c address h0ba), cpu address 510 accessed by serial in terface and i2c (r/w) 13.7.18 c2rs ? class 2 reserve size i2c address h0bb, cpu address 511 accessed by serial in terface and i2c (r/w) buffer reservation for class 2 (third lowest priority). granularity 1. (default 0) 7430 buffer low threshold sp buffer reservation bit [3:0]: per source port buffer reservation. define the space in the fdb reserved for each gigabit port. expressed in multiples of 16 packets. for each packet 1536 bytes are reserved in the memory. bits [7:4]: expressed in multiples of 16 packets. threshold for dropping all best effort frames when destination port best effort queues reach ucc threshold, shared pool is all used and source port reservation is at or below the prg [7:4] level. also the threshold for initiating uc flow control. ?default: - h58 for memory 2 mb/bank; - h35 for 1 mb/bank; 70 shared pool buffer size bits [7:0]: expressed in multiples of 4 packets. buffer reservation for shared pool. ?default: - h64 for 16+2 configuration with memory of 2 mb/bank; - h14 for 16+2 configuration with memory of 1 mb/bank; 70 class 2 fcb reservation ZL50417 data sheet 61 zarlink semiconductor inc. 13.7.19 c3rs ? class 3 reserve size i2c address h0bc, cpu address 512 accessed by serial in terface and i2c (r/w) buffer reservation for class 3. granularity 1. (default 0) 13.7.20 c4rs ? class 4 reserve size i2c address h0bd, cpu address 513 accessed by serial in terface and i2c (r/w) buffer reservation for class 4. granularity 1. (default 0) 13.7.21 c5rs ? class 5 reserve size i2c address h0be; cpu address 514 accessed by serial in terface and i2c (r/w) buffer reservation for class 5. granularity 1. (default 0) 13.7.22 c6rs ? class 6 reserve size i2c address h0bf; cpu address 515 accessed by serial in terface and i2c (r/w) buffer reservation for class 6 (second highest priority). granularity 1. (default 0) 70 class 3 fcb reservation 70 class 4 fcb reservation 70 class 5 fcb reservation 70 class 6 fcb reservation ZL50417 data sheet 62 zarlink semiconductor inc. 13.7.23 c7rs ? class 7 reserve size i2c address h0c0; cpu address 516 accessed by serial in terface and i2c (r/w) buffer reservation for class 7 (hig hest priority). granularity 1. (default 0) 13.7.24 qoscn - classes byte limit set 0 accessed by serial in terface and i2c (r/w): c ? qosc00 ? byte_c01 (i2c address h0c1, cpu address 517) b ? qosc01 ? byte_c02 (i2c address h0c2, cpu address 518) a ? qosc02 ? byte_c03 (i2c address h0c3, cpu address 519) qosc00 through qosc02 represents one set of values a-c for a 10/100 port when using the weighted random early drop (wred) scheme described in chapter 7. there ar e four such sets of values a-c specified in classes byte limit set 0, 1, 2, and 3. each 10/ 100 port can choose one of the four byte limit sets as specified by the qos select field located in bits 5 to 4 of the ecr2n register. the values a-c are per-queue byte thresholds for random early drop. qosc02 represents a, and qosc00 represents c. granularity when delay bound is used: qosc02: 128 byte s, qosc01: 256 bytes, qosc00: 512 bytes. granularity when wfq is used: qosc02: 512 bytes, qosc01: 512 bytes, qosc00: 512 bytes. 13.7.25 classes byte limit set 1 accessed by serial in terface and i2c (r/w): c - qosc03 ? byte_c11 (i2c address h0c4, cpu address 51a) b - qosc04 ? byte_c12 (i2c address h0c5, cpu address 51b) a - qosc05 ? byte_c13 (i2c address h0c6, cpu address 51c) qosc03 through qosc05 represents one set of values a-c for a 10/100 port when using the weighted random early detect (wred) scheme. granularity when delay bound is used: qosc05: 128 byte s, qosc04: 256 bytes. qosc03: 512 bytes. granularity when wfq is used: qosc05: 512 bytes, qosc04: 512 bytes, qosc03: 512 bytes. 13.7.26 classes byte limit set 2 accessed by serial interface (r/w): c - qosc06 ? byte_c2 1 (cpu address 51d) b - qosc07 ? byte_c22 (cpu address 51e) a - qosc08 ? byte_c23 (cpu address 51f) 70 class 7 fcb reservation ZL50417 data sheet 63 zarlink semiconductor inc. qosc06 through qosc08 represents one set of values a-c for a 10/100 port when using the weighted random early detect (wred) scheme. granularity when delay bound is used: qosc08: 128 byte s, qosc07: 256 bytes. qosc06: 512 bytes. granularity when wfq is used: qosc08: 512 bytes, qosc07: 512 bytes, qosc06: 512 bytes. 13.7.27 classes byte limit set 3 accessed by serial interface (r/w): c - qosc09 ? byte_c31 (cpu address 520) b - qosc10 ? byte_c32 (cpu address 521) a - qosc11 ? byte_c33 (cpu address 522) qosc09 through qosc011 represents one set of values a-c for a 10/100 port when using the weighted random early drop (wred) scheme. granularity when delay bound is used: qosc11: 128 bytes, qosc10: 256 bytes, qosc09: 512 bytes. granularity when wfq is used: qosc11: 512 bytes, qosc10: 512 bytes, qosc09: 512 bytes 13.7.28 classes byte limit giga port 1 accessed by serial in terface and i2c (r/w): f - qosc12 ? byte_c2_g1 (i2c address h0c7, cpu address 523) e - qosc13 ? byte_c3_g1 (i2c address h0c8, cpu address 524) d - qosc14 ? byte_c4_g1 (i2c address h0c9, cpu address 525) c -qosc15 ? byte_c5_g1 (i2c address h0ca, cpu address 526) b - qosc16 ? byte_c6_g1 (i2c address h0cb, cpu address 527) a - qosc17 ? byte_c7_g1 (i2c address h0cc, cpu address 528) qosc12 through qosc17 represent the values a-f for gigabit port 1. they are per-queue byte thresholds for random early drop. qosc17 represents a, and qosc12 represents f. granularity when delay bound is used: qosc17 and qosc16: 256 bytes, qosc15 and qosc14: 512 bytes, qosc13 and qosc12: 1024 bytes. granularity when wfq is used: qosc17 to qosc12: 1024 bytes 13.7.29 classes byte limit giga port 2 accessed by serial in terface and i2c (r/w) f - qosc18 ? byte_c2_g2 (i2c address h0cd, cpu address 529) e - qosc19 ? byte_c3_g2 (i2c address h0ce, cpu address 52a) d - qosc20 ? byte_c4_g2 (i2c address h0cf, cpu address 52b) c - qosc21 ? byte_c5_g2 (i2c address h0d0, cpu address 52c) b - qosc22 ? byte_c6_g2 (i2c address h0d1, cpu address 52d) a - qosc23 ? byte_c7_g2 (i2c address h0d2, cpu address 52e) ZL50417 data sheet 64 zarlink semiconductor inc. qosc12 through qosc17 represent the values a-f for gigabit port 2. they are per-queue byte thresholds for random early drop. qosc17 represents a, and qosc12 represents f. granularity when delay bound is used: qosc17 and qosc16: 256 bytes, qosc15 and qosc14: 512 bytes, qosc13 and qosc12: 1024 bytes. granularity when wfq is used: qosc17 to qosc12: 1024 bytes 13.7.30 classes wfq credit set 0 accessed by serial interface w0 - qosc24[5:0] ? credit_c00 (cpu address 52f) w1 - qosc25[5:0] ? credit_c01 (cpu address 530) w2 - qosc26[5:0] ? credit_c02 (cpu address 531) w3 - qosc27[5:0] ? credit_c03 (cpu address 532) qosc24 through qosc27 represents one set of wfq parameters for a 10/100 port. there are four such sets of values. the granularity of the numbers is 1, and their sum must be 64. qosc27 corresponds to w3, and qosc24 corresponds to w0. qosc24[7:6]: priority service type for the ports select this parame ter set. option 1 to option 4. qosc25[7]: priority service a llow flow control for the port s select this parameter set. qosc25[6]: flow control pause best effort traffic only both flow control allow and flow control best effort only can take effect only the priority type is wfq. 13.7.31 classes wfq credit set 1 accessed by serial interface w0 - qosc28[5:0] ? credit_c10 (cpu address 533) w1 - qosc29[5:0] ? credit_c11 (cpu address 534) w2 - qosc30[5:0] ? credit_c12 (cpu address 535) w3 - qosc31[5:0] ? credit_c13 (cpu address 536) qosc28 through qosc31 represents one set of wfq parameters for a 10/100 port. there are four such sets of values. the granularity of the numbers is 1, and their sum must be 64. qosc31 corresponds to w3, and qosc28 corresponds to w0. qosc28[7:6]: priority service type for the ports select this parame ter set. option 1 to option 4. qosc29[7]: priority service a llow flow control for the port s select this parameter set. qosc29[6]: flow control pause best effort traffic only 13.7.32 classes wfq credit set 2 accessed by serial interface w0 - qosc32[5:0] ? credit_c20 (cpu address 537) w1 - qosc33[5:0] ? credit_c21 (cpu address 538) ZL50417 data sheet 65 zarlink semiconductor inc. w2 - qosc34[5:0] ? credit_c22 (cpu address 539) w3 - qosc35[5:0] ? credit_c23 (cpu address 53a) qosc35 through qosc32 represents one set of wfq parameters for a 10/100 port. there are four such sets of values. the granularity of the numbers is 1, and their sum must be 64. qosc35 corresponds to w3, and qosc32 corresponds to w0. qosc32[7:6]: priority service type for the ports select this parame ter set. option 1 to option 4. qosc33[7]: priority service a llow flow control for the port s select this parameter set. qosc33[6]: flow control pause for best effort traffic only 13.7.33 classes wfq credit set 3 accessed by serial interface w0 - qosc36[5:0] ? credit_c30 (cpu address 53b) w1 - qosc37[5:0] ? credit_c31 (cpu address 53c) w2 - qosc38[5:0] ? credit_c32 (cpu address 53d) w3 - qosc39[5:0] ? credit_c33 (cpu address 53e) qosc39 through qosc36 represents one set of wfq parameters for a 10/100 port. there are four such sets of values. the granularity of the numbers is 1, and their sum must be 64. qosc39 corresponds to w3, and qosc36 corresponds to w0. qosc36[7:6]: priority service type for the ports select this parame ter set. option 1 to option 4. qosc37[7]: priority service a llow flow control for the port s select this parameter set. qosc37[6]: flow control pause best effort traffic only 13.7.34 classes wfq credit port g1 accessed by serial interface w0 - qosc40[5:0] - credit_c0_g1(cpu address 53f) [7:6]: priority servic e type. option 1 to 4. w1 - qosc41[5:0] ? credit_c1_g1 (cpu address 540) [7]: priority service allow flow control for the ports select this parameter set. [6]: flow control pause best effort traffic only w2 - qosc42[5:0] ? credit_c2_g1 (cpu address 541) w3 - qosc43[5:0] ? credit_c3_g1 (cpu address 542) w4 - qosc44[5:0] ? credit_c4_g1 (cpu address 543) w5 - qosc45[5:0] ? credit_c5_g1 (cpu address 544) w6 - qosc46[5:0] ? credit_c6_g1 (cpu address 545) w7 - qosc47[5:0] ? credit_c7_g1 (cpu address 546) qosc40 through qosc47 represents the set of wfq parame ters for gigabit port 24. the granularity of the numbers is 1, and their sum must be 64. qosc47 corresponds to w7, and qosc40 corresponds to w0. ZL50417 data sheet 66 zarlink semiconductor inc. 13.7.35 classes wfq credit port g2 accessed by serial interface w0 - qosc48[5:0] ? credit_c0_g2(cpu address 547) [7:6]: priority serv ice type. option 1 to 4 w1 - qosc49[5:0] ? credit_c1_g2(cpu address 548) [7]: priority service allow flow control for the ports select this parameter set. [6]: flow control pause best effort traffic only w2 - qosc50[5:0] ? credit_c2_g2(cpu address 549) w3 - qosc51[5:0] ? credit_c3_g2(cpu address 54a) w4 - qosc52[5:0] ? credit_c4_g2(cpu address 54b) w5 - qosc53[5:0] ? credit_c5_g2(cpu address 54c) w6 - qosc54[5:0] ? credit_c6_g2(cpu address 54d) w7 - qosc55[5:0] ? credit_c7_g2(cpu address 54e) qosc48 through qosc55 represents the set of wfq para meters for gigabit port 2. the granularity of the numbers is 1, and their sum must be 64. qosc55 corresponds to w7, and qosc48 corresponds to w0. 13.7.36 class 6 shaper control port g1 accessed by serial interface qosc56[5:0] ? token_rate_g1 (cpu address 54f). program s de average rate for gigabit port 1. when equal to 0, shaper is disable. granularity is 1. qosc57[7:0] ? token_limit_g1 (cpu address 550). programs the maximum c ounter for gigabit port 1. granularity is 16 bytes. shaper is implemented to control the peak and average rate for outgoing traffic with priority 6 (queue 6). shaper is limited to gigabit ports and queue p6 when it is in strict priority. qosc41 programs the peak rate for gigabit port 1. see programming qos registers application note for more information 13.7.37 class 6 shaper control port g2 accessed by serial interface qosc58[5:0] ? token_rate_g2 (cpu address 551). programs de average rate for gigabit port 2. when equal to 0, shaper is disable. granularity is 1. qosc59[7:0] ? token_limit_g2 (cpu address 552). programs the maximum c ounter for gigabit port 2. granularity is 16 bytes. shaper is implemented to control the peak and average rate for outgoing traffic with priority 6 (queue 6). shaper is limited to gigabit ports and queue p6 when it is in strict priority. qosc49 programs the peak rate for gigabit port 2. see programming qos register applic ation note for more information. ZL50417 data sheet 67 zarlink semiconductor inc. 13.7.38 rdrc0 ? wred rate control 0 i2c address 0fb, cpu address 553 accessed by serial interface and i c c (r/w) 13.7.39 rdrc1 ? wred rate control 1 i2c address 0fc, cpu address 554 accessed by serial interface and i2c (r/w) 13.7.40 user defined logical ports and well known ports the ZL50417 supports classifying packet priority through layer 4 logical port information. it can be setup by 8 well known ports, 8 user defined logical ports, and 1 user defined range. the 8 well known ports supported are: ?0:23 ?1:512 ?2:6000 ?3:443 ?4:111 ? 5:22555 ?6:22 ?7:554 their respective priority can be programmed via well_kno wn_port [7:0] priority register. well_known_port_ enable can individually turn on/off each well known port if desired. 7430 x rate y rate bits [7:4]: corresponds to the frame drop percentage x% for wred. granularity 6.25%. bits [3:0]: corresponds to the frame drop percentage y% for wred. granularity 6.25%. see programming qos registers application note for more information 7430 z rate b rate bits [7:4]: corresponds to the frame drop percentage z% for wred. granularity 6.25%. bits [3:0]: corresponds to the best effort frame drop percentage b%, when shared pool is all in use and destination port best effort queue reaches ucc. granularity 6.25%. see programming qos registers application note for more information ZL50417 data sheet 68 zarlink semiconductor inc. similarly, the user defined logical port provides the user programmability to the priority, plus the flexibility to select specific logical ports to fit the applications. the 8 user logical ports can be programmed via user_port 0-7 registers. two registers are required to be programmed fo r the logical port number. the respective priority can be programmed to the user_port [7:0] priority register. the port priority can be individually enabled/disabled via user_port_enable register. the user defined range provides a range of logical port numbers with the same priority level. programming is similar to the user defined logical port. instead of programming a fixed port number, an upper and lower limit need to be programmed, they are: {rhighh, rhighl} and {rlowh , rlowl} respectively. if the value in the upper limit is smaller or equal to the lower limit, the function is disabled. any ip packet with a logical port that is less than the upper limit and more than the lower limit will use the priority specified in rpriority. 13.7.40.1 user_port0_(0~7) ? user define logical port (0~7) user_port_0 - i2c address h0d6 + 0de; cpu address 580(low) + 581(high) user_port_1 - i2c address h0d7 + 0df; cpu address 582 + 583 user_port_2 - i2c address h0d8 + 0e0; cpu address 584 + 585 user_port_3 - i2c address h0d9 + 0e1; cpu address 586 + 587 user_port_4 - i2c address h0da + 0e2; cpu address 588 + 589 user_port_5 - i2c address h0db + 0e3; cpu address 58a + 58b user_port_6 - i2c address h0dc + 0e4; cpu address 58c + 58d user_port_7 - i2c address h0dd + 0e5; cpu address 58e + 58f accessed by cpu, serial interface and i2c (r/w) (default 00) this register is duplicated eight times fr om port 0 through port 7 and allows the cpu to define eight separate ports. 13.7.40.2 user_port_[1:0]_priority - u ser define logic port 1 and 0 priority i2c address h0e6, cpu address 590 accessed by serial in terface and i2c (r/w) the chip allows the cpu to define the priority 70 tcp/udp logic port low 70 tcp/udp logic port high 7543 10 priority 1 drop priority 0 drop bits [3:0]: priority setting, transmission + dropping, for logic port 0 bits [7:4]: priority setting, transmission + dropping, for logic port 1 (default 00) ZL50417 data sheet 69 zarlink semiconductor inc. 13.7.40.3 user_port_[3:2]_priority - u ser define logic port 3 and 2 priority i2c address h0e7, cpu address 591 accessed by serial in terface and i2c (r/w) 13.7.40.4 user_port_[5:4]_priority - u ser define logic port 5 and 4 priority i2c address h0e8, cpu address 592 accessed by serial in terface and i2c (r/w) (default 00) 13.7.40.5 user_port_[7:6]_priority - u ser define logic port 7 and 6 priority i2c address h0e9, cpu address 593 accessed by serial in terface and i2c (r/w) (default 00) 13.7.40.6 user_port_enable[7:0] ? u ser define logic 7 to 0 port enables i2c address h0ea, cpu address 594 accessed by serial in terface and i2c (r/w) (default 00) 754310 priority 3 drop priority 2 drop 754310 priority 5 drop priority 4 drop 754310 priority 7 drop priority 6 drop 7654 3 2 10 p7 p6 p5 p4 p3 p2 p1 p0 ZL50417 data sheet 70 zarlink semiconductor inc. 13.7.40.7 well_known_port[1:0] priority- well known logic port 1 and 0 priority i2c address h0eb, cpu address 595 accessed by serial in terface and i2c (r/w) priority 0 - well known port 23 for telnet applications. priority 1 - well known port 512 for tcp/udp. (default 00) 13.7.40.8 well_known_port[3:2] priority- well known logic port 3 and 2 priority i2c address h0ec, cpu address 596 accessed by serial in terface and i2c (r/w) priority 2 - well known port 6000 for xwin. priority 3 - well known port 443 for http.sec (default 00) 13.7.40.9 well_known_port [5:4] priority - well known logic port 5 and 4 priority i2c address h0ed, cpu address 597 accessed by serial in terface and i2c (r/w) priority 4 - well known port 111 for sun remote procedure call. priority 5 - well known port 22555 for ip phone call setup. (default 00) 13.7.40.10 well_known_port [7:6] priority - well known logic port 7 and 6 priority i2c address h0ee, cpu address 598 accessed by serial in terface and i2c (r/w) priority 6 - well know port 22 for ssh. priority 7 ? well known port 554 for rtsp. (default 00) 754310 priority 1 drop priority 0 drop 754310 priority 3 drop priority 2 drop 754310 priority 5 drop priority 4 drop 754310 priority 7 drop priority 6 drop ZL50417 data sheet 71 zarlink semiconductor inc. 13.7.40.11 well known_port_enable [7:0] ? well known logic 7 to 0 port enables i2c address h0ef, cpu address 599 accessed by serial in terface and i2c (r/w) - 1 ? enable - 0 - disable (default 00) 13.7.40.12 rlowl ? user define range low bit 7:0 i2c address h0f4, cpu address: 59a accessed by serial in terface and i2c (r/w) (default 00) 13.7.40.13 1rlowh ? user define range low bit 15:8 i2c address h0f5, cpu address: 59b accessed by serial in terface and i2c (r/w) (default 00) 13.7.40.14 rhighl ? user define range high bit 7:0 i2c address h0d3, cpu address: 59c accessed by cpu, serial interface and i2c (r/w) (default 00) 13.7.40.15 rhighh ? user define range high bit 15:8 i2c address h0d4, cpu address: 59d accessed by serial in terface and i2c (r/w) (default 00) 13.7.40.16 rpriority ? user define range priority i2c address h0d5, cpu address: 59e accessed by serial in terface and i2c (r/w) 7654 3 2 10 p7 p6 p5 p4 p3 p2 p1 p0 743 0 range transmit priority drop ZL50417 data sheet 72 zarlink semiconductor inc. rlow and rhigh form a range for logical ports to be classified with priority specified in rpriority. 13.8 (group 6 address) misc group 13.8.1 mii_op0 ? mii register option 0 i2c address f0, cpu address:h600 accessed by serial in terface and i2c (r/w) 13.8.2 mii_op1 ? mii register option 1 i2c address f1, cpu address:h601 accessed by serial in terface and i2c (r/w) bit [3:1] trans mit priority bits [0]: drop priority 76 5 4 0 hfc 1prst disj vendor spc. reg addr bits [7]: half duplex flow control feature 0 = half duplex flow control always enable 1 = half duplex flow control by negotiation bits [6]: link partner rese t auto-negotia te disable bits [5]: disable jabber detection. this is for homepna applications or any serial operation slower than 10 mbps. 0 = enable 1 = disable bit [4:0]: vendor specified link status register address (null value means don?t use it) (default 00). this is used if the linkup bit position in the phy is non-standard 743 0 speed bit location duplex bit location bits [3:0]: duplex bi t location in vendor specified register bits [7:4]: speed bit location in vendor specified register (default 00) ZL50417 data sheet 73 zarlink semiconductor inc. 13.8.3 fen ? feature register i2c address f2, cpu address:h602) accessed by serial in terface and i2c (r/w) 13.8.4 miic0 ? mii command register 0 cpu address:h603 accessed by serial in terface only (r/w) bit [7:0] - mii data [7:0] note : before programming mii command: set fen[6], check miic3, making sure no rdy, and no valid; then program mii command. 13.8.5 miic1 ? mii command register 1 cpu address:h604 accessed by serial in terface only (r/w) bit [7:0] - mii data [15:8] note : before programming mii command: set fen[6], check miic3, making sure no rdy and no valid; then program mii command. 765 3 21 0 dml mii ds bits [1:0]: reserved (default 0) bit [2]: support ds ef code. (default 0) - 0 ? disable - 1 ? enable (all ports) when 101110 is detected in ds field (tos[7:2]), the frame priority is set for 110 and drop is set for 0. bit [5:3]: reserved (default 010) bit [6]: disable mii management state machine (default 0) - 0: enable mii management state machine - 1: disable mii management state machine bit [7]: disable using mct link list structure (default 0) - 0 ? enable using mct link structure - 1 - disable using mct link list structure ZL50417 data sheet 74 zarlink semiconductor inc. 13.8.6 miic2 ? mii command register 2 cpu address:h605 accessed by serial in terface only (r/w) note: before programming mii command: set fen[6], check miic3, making sure no rdy and no valid; then program mii command. 13.8.7 miic3 ? mii command register 3 cpu address:h606 accessed by serial in terface only (r/w) note : before programming mii command: set fen[6], check miic3, making sure no rdy and no valid; then program mii command. wr iting this register will initiate a serial management cycle to the mii management interface. 13.8.8 miid0 ? mii data register 0 cpu address:h607 accessed by serial interface only (ro) bit [7:0] - mii data [7:0] 13.8.9 miid1 ? mii data register 1 cpu address:h608 accessed by serial interface only (ro) bit [7:0] - mii data [15:8] 76 54 0 mii op register address - bit [4:0] reg_ad ? register phy address - bit [6:5] op ? operation code ?10? fo r read command and ?01? for write command 7654 0 rdy valid phy address - bits [4:0] phy_ad ? 5 bit phy address - bit [6] valid ? data valid from phy (read only) - bit [7] rdy ? data is returned from phy (ready only) ZL50417 data sheet 75 zarlink semiconductor inc. 13.8.10 led mode ? led control cpu address:h609 accessed by cpu, serial interface and i2c (r/w) 13.8.11 checksum - eeprom checksum i2c address ff, cpu address:h60b accessed by serial in terface and i2c (r/w) this register is used in un managed mode only. be fore requesting that the zl50 417 updates the eeprom device, the correct checksum needs to be calculated and written into this checksum register . the checksum formula is: ff i2c register = 0 i = 0 when the zl5041 7 boots from the eeprom the checksum is calc ulated and the value must be zero. if the checksum is not zeroed the zl 50417 does not start and pin checksum_ok is set to zero. 7543210 clock rate hold time - bit [0] reserved (default 0) - bit [2:1]: hold ti me for led signal (default 00) 00 = 8 msec 01 = 16 msec 10 = 32 msec 11 = 64 msec - bit [4:3]: led clock frequency (default 0) 00 = 100 m/8 = 12.5 mhz 01 = 100 m/16 = 25 mhz 10 = 100 m/32 = 125 mhz 11 = 100 m/64 =1.5625 mhz - bit [7:5]: reserved. must be set to ?0? (default 0) - bit [7:0]: (default 0) ZL50417 data sheet 76 zarlink semiconductor inc. 13.9 (group 7 address) port mirroring group 13.9.1 mirror1_src ? port mirror source port cpu address 700 accessed by serial interface (r/w) (default 7f) 13.9.2 mirror1_dest ? port mirror destination cpu address 701 accessed by serial interface (r/w) (default 17) 13.9.3 mirror2_src ? port mirror source port cpu address 702 accessed by serial interface (r/w) (default ff) 7654 0 i/o src port select - bit [4:0]: source port to be mirrored. use illegal port number to disable mirroring - bit [5]: 1 ? select ingress data 0 ? select egress data - bit [6]: reserved - bit [7]: reserved mu st be se to '1' 754 0 dest port select - bit [4:0]: port mirror destination when port mirroring is enable, destination port can not serve as a data port. 7654 0 i/o src port select - bit [4:0]: source port to be mirrored. us e illegal port number to disable mirroring - bit [5]: 1 ? select ingress data 0 ? select egress data - bit [6] reserved - bit [7] reserved must be set to '1' ZL50417 data sheet 77 zarlink semiconductor inc. 13.9.4 mirror2_dest ? port mirror destination cpu address 703 accessed by serial interface (r/w) (default 00) 13.10 (group f address) cpu access group 13.10.1 gcr-global control register cpu address: hf00 accessed by serial interface. (r/w) 13.10.2 dcr-device status and signature register cpu address: hf01 accessed by serial interface. (ro) 754 0 dest port select bit [4:0]: port mi rror destination when port mirroring is enable, destination port can not serve as a data port. 7 43 210 reset bist sr sc bit [0]: store configuration (default = 0) write ?1? followed by ?0? to store configuration into external eeprom bit [1]: store configuration and reset (default = 0) write ?1? to store configuration in to external eeprom and reset chip bit [2]: start bist (default = 0) write ?1? followed by ?0? to start the device?s built-in self-test. the result is found in the dcr register. bit [3]: soft reset (default = 0) write ?1? to reset chip bit [7:4]: reserved 76543210 revision signature re binp br bw bit [0]: 1: busy writing configuration to i2c 0: not busy (not writing configuration to i2c) bit [1]: 1: busy reading configuration from i2c 0: not busy (not reading configuration from i2c) ZL50417 data sheet 78 zarlink semiconductor inc. 13.10.3 dcr1-giga port status cpu address: hf02 accessed by serial interface. (ro) 13.10.4 dpst ? device port status register cpu address:hf03 accessed by serial interface (r/w) bit [2]: 1: bist in progress 0: bist not running bit [3]: 1: ram error 0: ram ok bit [5:4]: device signature 11: ZL50417 device bit [7:6]: revision 00: initial silicon 01: xa1 silicon 10: production silicon 76 43210 cic giga1 giga0 bit [1:0]: giga port 0 strap option - 00 ? 100 mb mii mode - 01 ? reserved -10 ? gmii - 11 ? pcs bit [3:2] giga port 1 strap option - 00 ? 100 mb mii mode - 01 ? reserved -10 ? gmii - 11 ? pcs bit [7] chip initiali zation completed bit [4:0]: read back index register. this is used for selecting what to read back from dtst. (default 00) - 5?b00000 - port 0 operating mode and negotiation status - 5?b00001 - port 1 operating mode and negotiation status - 5?b00010 - port 2 operating mode and negotiation status ZL50417 data sheet 79 zarlink semiconductor inc. 13.10.5 dtst ? data read back register cpu address: hf04 accessed by serial interface (ro) this register provides various internal information as selected in dpst bit [4:0]. refer to the phy control application note. - 5?b00011 - port 3 operating mode and negotiation status - 5?b00100 - port 4 operating mode and negotiation status - 5?b00101 - port 5 operating mode and negotiation status - 5?b00110 - port 6 operating mode and negotiation status - 5?b00111 - port 7 operating mode and negotiation status - 5?b01000 - port 8 operating mode and negotiation status - 5?b01001 - port 9 operating mode and negotiation status - 5?b01010 - port 10 operating mode and negotiation status - 5?b01011 - port 11 operating mode and negotiation status - 5?b01100 - port 12 operating mode and negotiation status - 5?b01101 - port 13 operating mode and negotiation status - 5?b01110 - port 14 operating mode and negotiation status - 5?b01111 - port 15 operating mode and negotiation status - 5?b10000 - reserved - 5?b10001 - reserved - 5?b10010 - reserved - 5?b00011 - reserved - 5?b10100 - reserved - 5?b10101 - reserved - 5?b10110 - reserved - 5?b10111 - reserved - 5?b11000 - reserved - 5?b11001 - port 25 operating mode/neg status (gigabit 1) - 5?b11010 - port 26 operating mode/neg status (gigabit 2) 7 654321 0 md sig giga inkdn fe fdpx fcen ZL50417 data sheet 80 zarlink semiconductor inc. when bit is 1: bit [0] ? flow control enable bit [1] ? full duplex port bit [2] ? fast ethernet port (if not gigabit port) bit [3] ? link is down bit [4] ? giga port bit [5] ? signal detect (when pcs interface mode) bit [6] - reserved bit [7] ? module detected (for hot swap purpose) 13.10.6 pllcr - pll control register cpu address: hf05 accessed by serial interface (rw) bit [3] - must be '1' bit [7] - selects strap opti on or lclk/oeclk registers 0 - strap option (default) 1 - lclk/oeclk registers 13.10.7 lclk - la_clk delay from internal oe_clk cpu address: hf06 accessed by serial interface (rw) pd[12:10] lclk delay 000b 80h 8 buffers delay 001b 40h 7 buffers delay 010b 20h 6 buffers delay 011b 10h 5 buffers delay (recommend) 100b 08h 4 buffers delay 101b 04h 3 buffers delay 110b 02h 2 buffers delay 111b 01h 1 buffers delay the lclk delay from sclk is the sum of the delay programmed in here and the delay in oeclk register. ZL50417 data sheet 81 zarlink semiconductor inc. 13.10.8 oeclk - internal oe_clk delay from sclk cpu address: hf07 accessed by serial interface (rw) the oe_clk is used for generating the oe0 and oe1 signals. pd[15:13] oeclk delay 000b 80h 8 buffers delay 001b 40h 7 buffers delay (recommend) 010b 20h 6 buffers delay 011b 10h 5 buffers delay 100b 08h 4 buffers delay 101b 04h 3 buffers delay 110b 02h 2 buffers delay 111b 01h 1 buffers delay 13.10.9 da ? da register cpu address: hfff accessed by serial interface (ro) always return 8?h da . indicate the serial port connection is good. 13.11 tbi registers two sets of tbi registers are used for configure the two gi gabit ports if they are operating in tbi mode. these tbi registers are located inside the switching chip and they are accessed through the mii command and mii data registers. ZL50417 data sheet 82 zarlink semiconductor inc. 13.11.1 control register mii address: h00 read/write 13.11.2 status register mii address: h01 read only bit [15] reset pcs logic and all tbi registers 1 = reset 0 = normal operation bit [14] reserved. must be programmed with ?0?. bit [13] speed selection (see bit 6 for complete details) bit [12] auto negotiation enable 1 = enable auto-negotiation process. 0 = disable auto-negotiation process (default) bit [11:10] reserved. must be programmed with ?0? bit [9] restart auto negotiation. 1 = restart auto-negotiation process. 0 = normal operation (default). bit [8:7] reserved. bit [6] speed selection bit [6] [13] 1 1 = reserved 0 =1000 mb/s (default) 1 =100 mb/s 0 0 =10 mb/s bit [5:0] reserved. must be programmed with ?0?. bit [15:9] reserved. al ways read back as ?0?. bit [8] reserved. alwa ys read back as ?1?. bit [7:6] reserved. al ways read back as ?0?. bit [5] auto-negotiation complete 1 = auto-negotiation process completed. 0 = auto-negotiation process not completed. bit [4] reserved. alwa ys read back as ?0? bit [3] reserved. alwa ys read back as ?1? bit [2] link status 1 = link is up. 0 = link is down. bit [1] reserved. alwa ys read back as ?0?. bit [0] reserved. alwa ys read back as ?1?. ZL50417 data sheet 83 zarlink semiconductor inc. 13.11.3 advertisement register mii address: h04 read/write 13.11.4 link partner ability register mii address: h05 read only bit [15] next page 1 = has next page capabilities. 0 = do not has next page capabilities (default). bit [14] reserved. always read back as ?0?. read only. bit [13:12] remote fault. default is ?0?. bit [11:9] reserved. always read back as ?0?. read only. bit [8:7] pause. default is ?00? bit [6] half duplex 1 = support half duplex (default). 0 = do not support half duplex. bit [5] full duplex 1 = support full duplex (default). 0 = do not support full duplex. bit [4:0] reserved. always read back as ?0?. read only. bit [15] next page 1 = has next page capabilities. 0 = do not has next page capabilities. bit [14] acknowledge bit [13:12] remote fault. bit [11:9] reserved. always read back as ?0?. bit [8:7] pause. bit [6] half duplex 1 = support half duplex. 0 = do not support half duplex. bit [5] full duplex 1 = support full duplex. 0 = do not support full duplex. bit [4:0] reserved. al ways read back as ?0?. ZL50417 data sheet 84 zarlink semiconductor inc. 13.11.5 expansion register mii address: h06 read only 13.11.6 extended status register mii address: h15 read only bit [15:2] reserved. al ways read back as ?0?. bit [1] page received. 1 = a new page has been received. 0 = a new page has not been received. bit [0] reserved. alwa ys read back as ?0?. bit [15] 1000 full duplex 1 = support 1000 full duplex operation (default). 0 = do not support 1000 full duplex operation. bit [14] 1000 half duplex 1 = support 1000 half duplex operation (default). 0 = do not support 1000 half duplex operation. bit [13:0] reserved. al ways read back as ?0?. ZL50417 data sheet 85 zarlink semiconductor inc. 14.0 bga and ball signal descriptions 14.1 bga views (top-view) 1 234567891011121314151617181920212223242526272829 ala_d 4 la_d 7 la_d 10 la_d 13 la_d 15 la_a 4 la_o e0_ la_a 8 la_a 13 la_a 16 la_a 19 la_d 33 la_d 36 la_d 39 la_d 42 la_d 45 oe_ clk0 la_ clk0 trun k1 rese rved rese rved scl sda stro be tsto ut7 bla_d 1 la_d 3 la_d 6 la_d 9 la_d 12 la_d 14 la_a dsc_ la_o e1_ la_a 7 la_a 12 la_a 15 la_a 18 la_d 32 la_d 35 la_d 38 la_d 41 la_d 44 oe_ clk1 la_ clk1 la_d 62 rese rved rese rved trun k2 rese rved d0 tsto ut8 tsto ut3 cla_c lk la_d 0 la_d 2 la_d 5 la_d 8 la_d 11 la_a 3 la_o e_ la_w e_ t_mo de1 la_a 11 la_a 14 la_a 17 la_a 20 la_d 34 la_d 37 la_d 40 la_d 43 oe_ clk2 la_ clk2 p_d trun k0 rese rved rese rved auto fd tsto ut11 tsto ut9 tsto ut4 tsto ut0 d agn d la_d 17 la_d 19 la_d 21 la_d 23 la_d 25 la_d 27 la_d 29 la_d 31 la_a 6 la_a 10 la_w e0_ la_d 49 la_d 51 la_d 53 la_d 55 la_d 57 la_d 59 la_d 61 la_d 63 la_d 47 scan col scan clk tsto ut14 tsto ut13 tsto ut12 tsto ut10 tsto ut5 tsto ut1 esclk la_d 16 la_d 18 la_d 20 la_d 22 la_d 24 la_d 26 la_d 28 la_d 30 la_a 5 la_a 9 la_w e1_ la_d 48 la_d 50 la_d 52 la_d 54 la_d 56 la_d 58 la_d 60 rese rved la_d 46 scan link tsto ut15 m26_ crs m26_ txer scan mod tsto ut6 tsto ut2 f av c c resi n_ scan en lb_d 63 lb_d 62 vcc vcc vcc vcc vcc m26_ txcl m26_ txen m26_ mtx- m26_ rxdv m26_ rxcl g lb_c lk rese tout lb_d 47 lb_d 61 lb_d 60 rese rved rese rved rese rved m26_ rxer m26_ col hlb_d 46 lb_d 45 lb_d 44 lb_d 59 lb_d 58 rese rved rese rved rese rved rese rved rese rved jlb_d 43 lb_d 42 lb_d 41 lb_d 57 lb_d 56 rese rved rese rved m26_ rxd9 rese rved rese rved klb_d 40 lb_d 39 lb_d 38 lb_d 55 lb_d 54 vdd vdd vdd vdd m26_ txd9 m26_ txd8 m26_ rxd6 m26_ rxd7 m26_ rxd8 llb_d 37 lb_d 36 lb_d 35 lb_d 53 lb_d 52 m26_ txd4 m26_ txd6 m26_ rxd3 m26_ rxd4 m26_ rxd5 mlb_d 34 lb_d 33 lb_d 32 lb_d 51 lb_d 50 vdd vss vss vss vss vss vss vss vdd m26_ txd7 m26_ txd5 m26_ rxd0 m26_ rxd1 m26_ rxd2 nlb_a 18 lb_a 19 lb_a 20 lb_d 49 lb_d 48 vcc vdd vss vss vss vss vss vss vss vdd vcc m26_ txd2 m26_ txd3 gref _clk plb_a 15 lb_a 16 lb_a 17 lb_w e0_ lb_w e1_ vcc vss vss vss vss vss vss vss vcc m26_ txd0 m26_ txd1 mdio gref _clk rlb_a 10 lb_a 11 lb_a 12 lb_a 13 lb_a 14 vcc vss vss vss vss vss vss vss vcc m25_ crs m25_ txer mdc m_cl k tlb_a 5 lb_a 6 lb_a 7 lb_a 8 lb_a 9 vcc vss vss vss vss vss vss vss vcc m25_ txcl m25_ txen m25_ mtx- m25_ rxdv m25_ rxcl ulb_o e0_ lb_o e1_ t_mo de0 lb_d 31 lb_d 30 vcc vdd vss vss vss vss vss vss vss vdd vcc rese rved rese rved rese rved m25_ rxer m25_ col vlb_a dsc_ lb_o e_ lb_w e_ lb_d 29 lb_d 28 vdd vss vss vss vss vss vss vss vdd rese rved rese rved rese rved rese rved rese rved wlb_d 15 lb_a 3 lb_a 4 lb_d 27 lb_d 26 rese rved rese rved m25_ rxd9 rese rved rese rved ylb_d 14 lb_d 13 lb_d 12 lb_d 25 lb_d 24 vdd vdd vdd vdd m25_ rxd6 m25_ txd8 m25_ txd9 m25_ rxd7 m25_ rxd8 aa lb_d 11 lb_d 10 lb_d 9 lb_d 23 lb_d 22 m25_ txd6 m25_ txd7 m25_ rxd3 m25_ rxd4 m25_ rxd5 ab lb_d 8 lb_d 7 lb_d 6 lb_d 21 lb_d 20 m25_ txd4 m25_ txd5 m25_ rxd0 m25_ rxd1 m25_ rxd2 ac lb_d 5 lb_d 4 lb_d 3 lb_d 19 lb_d 18 m25_ txd2 m25_ txd3 rese rved rese rved rese rved ad lb_d 2 lb_d 1 lb_d 0 lb_d 17 lb_d 16 vcc vcc vcc vcc vcc m25_ txd0 m25_ txd1 rese rved rese rved rese rved ae m0_t xen m0_t xd0 m0_t xd1 m3_t xd1 m3_t xen m3_r xd0 m5_t xd1 m5_t xen m5_r xd0 m8_t xd1 m8_t xen m8_r xd0 m10_ txd1 m10_ txen m10_ rxd0 m13_ txd1 rese rved m15_ txd1 rese rved m15_ txen m15_ rxd0 rese rved rese rved rese rved rese rved rese rved rese rved rese rved af m0_r xd1 m0_r xd0 m0_c rs m3_t xd0 m3_c rs m3_r xd1 m5_t xd0 m5_c rs m5_r xd1 m8_t xd0 m8_c rs m8_r xd1 m10_ txd0 m10_ crs m10_ rxd1 m13_ txd0 m13_ crs m13_ rxd1 m14_ crs rese rved m15_ rxd1 rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved ag m1_t xen m1_t xd0 m1_t xd1 m2_t xd1 m2_c rs m4_t xd1 m4_c rs m6_t xd1 m6_c rs m7_t xd1 m7_c rs m9_t xd1 m9_c rs m11_ txd1 m11_ crs m12_ txd1 m12_ crs m14_ txd1 m15_ txd0 rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved rese rved ah m1_r xd0 m1_c rs m2_t xd0 m2_r xd0 m4_t xd0 m4_r xd0 m6_t xd0 m6_r xd0 m7_t xd0 m7_r xd0 m9_t xd0 m9_r xd0 m11_ txd0 m11_ rxd0 m12_ txd0 m12_ rxd0 m14_ txd0 m14_ rxd0 m13_ rxd0 m15_ crs rese rved rese rved rese rved rese rved rese rved rese rved rese rved aj m1_r xd1 m2_t xen m2_r xd1 m4_t xen m4_r xd1 m6_t xen m6_r xd1 m7_t xen m7_r xd1 m9_t xen m9_r xd1 m11_ txen m11_ rxd1 m12_ txen m12_ rxd1 m14_ txen m14_ rxd1 rese rved m13_ txen rese rved rese rved rese rved rese rved rese rved rese rved 1234567891011121314151617181920212223242526272829 ZL50417 data sheet 86 zarlink semiconductor inc. 14.1.1 ball signal descriptions ball no(s) symbol i/o description i2c interface note: use i2c and serial control interface to configure the system a24 scl output i2c data clock a25 sda i/o-ts with internal pull up i2c data i/o serial control interface a26 strobe input with weak internal pull up serial strobe pin b26 d0 input with weak internal pull up serial data input c25 autofd output with pull up serial data output (autofd) frame buffer interface d20, b21, d19, e19,d18, e18, d17, e17, d16, e16, d15, e15, d14, e14, d13, e13, d21, e21, a18, b18, c18, a17, b17, c17, a16, b16, c16, a15, b15, c15, a14, b14, d9, e9, d8, e8, d7, e7, d6, e6, d5, e5, d4, e4, d3, e3, d2, e2, a7, b7, a6, b6, c6, a5, b5, c5, a4, b4, c4, a3, b3, c3, b2, c2 la_d[63:0] i/o-ts with pull up frame bank a? data bit [63:0] c14, a13, b13, c13, a12, b12, c12, a11, b11, c11, d11, e11, a10, b10, d10, e10, a8, c7 la_a[20:3] output frame bank a ? address bit [20:3] b8 la_adsc# output with pull up frame bank a address status control c1 la_clk output with pull up frame bank a clock input c9 la_we# output with pull up frame bank a write chip select for one layer sram application d12 la_we0# output with pull up frame bank a write chip select for lower layer of two bank sram application e12 la_we1# output with pull up frame bank a write chip select for upper bank of two layer sram application ZL50417 data sheet 87 zarlink semiconductor inc. c8 la_oe# output with pull up frame bank a read chip select for one layer sram application a9 la_oe0# output with pull up frame bank a read chip select for lower layer of two layers sram application b9 la_oe1# output with pull up frame bank a read chip select for upper layer of two layers sram application f4, f5, g4, g5, h4, h5, j4, j5, k4, k5, l4, l5, m4, m5, n4, n5, g3, h1, h2, h3, j1, j2, j3, k1, k2, k3, l1, l2, l3, m1, m2, m3, u4, u5, v4, v5, w4, w5, y4, y5, aa4, aa5, ab4, ab5, ac4, ac5, ad4, ad5, w1, y1, y2, y3, aa1, aa2, aa3, ab1, ab2, ab3, ac1, ac2, ac3, ad1, ad2, ad3 lb_d[63:0] i/o-ts with pull up. frame bank b? data bit [63:0] n3, n2, n1, p3, p2, p1, r5, r4, r3, r2, r1, t5, t4, t3, t2, t1, w3, w2 lb_a[20:3] output frame bank b ? address bit [20:3] v1 lb_adsc# output with pull up frame bank b address status control g1 lb_clk output with pull up frame bank b clock input v3 lb_we# output with pull up frame bank b write chip select for one layer sram application p4 lb_we0# output with pull up frame bank b write chip select for lower layer of two layers sram application p5 lb_we1# output with pull up frame bank b write chip select for upper layer of two layers sram application v2 lb_oe# output with pull up frame bank b read chip select for one layer sram application u1 lb_oe0# output with pull up frame bank b read chip select for lower layer of two layers sram application u2 lb_oe1# output with pull up frame bank b read chip select for upper layer of two layers sram application ball no(s) symbol i/o description ZL50417 data sheet 88 zarlink semiconductor inc. fast ethernet access ports [15:0] rmii r28 m_mdc output mii management data clock ? (common for all mii ports [15:0]) p28 m_mdio i/o-ts with pull up mii management data i/o ? (common for all mii ports ? [15:0]) r29 m_clki input reference input clock af21, aj19 , af18, aj17, aj15, af15, aj13, af12, aj11, aj9, af9, aj7, af6, aj5, aj3, af1 m[15:0]_rxd[1] input with we ak internal pull up resistors. ports [15:0] ? receive data bit [1] ae21, ah19, ah20, ah17, ah15, ae15, ah13, ae12, ah11, ah9, ae9, ah7, ae6, ah5, ah2, af2 m[15:0]_rxd[0] input with we ak internal pull up resistors ports [15:0] ? receive data bit [0] ah21, af19, af17, ag17, ag15, af14, ag13, af11, ag11, ag9, af8, ag7, af5, ag5, ah3, af3 m[15:0]_crs_dv input wi th weak internal pull down resistors. ports [15:0] ? carrier sense and receive data valid ae20, aj18, aj21, aj16, aj14, ae14, aj12, ae11, aj10, aj8, ae8, aj6, ae5, aj4, ag1, ae1 m[15:0]_txen i/o- ts with pull up, slew ports [15:0] ? transmit enable strap option for rmii/gpsi ae18, ag18, ae16, ag16, ag14, ae13, ag12, ae10, ag10, ag8, ae7, ag6, ae4, ag4, ag3, ae3 m[15:0]_txd[1] output, slew port s [15:0] ? transmit data bit [1] ag19, ah18, af16, ah16, ah14, af13, ah12, af10, ah10, ah8, af7, ah6, af4, ah4, ag2, ae2 m[15:0]_txd[0] output, slew port s [15:0] ? transmit data bit [0] gmii/tbi gigabit ethernet access ports 0 & 1 y27, y26, aa26, aa25, ab26, ab25, ac26, ac25, ad26, ad25 m25_txd[9:0] output transmit data bit [9:0] t28 m25_rx_dv input w/ pulldown receive data valid u28 m25_rx_er input w/ pullup receive error r25 m25_crs input w/ pulldown carrier sense ball no(s) symbol i/o description ZL50417 data sheet 89 zarlink semiconductor inc. u29 m25_col input w/ pullup collision detected t29 m25_rxclk input w/ pullup receive clock w27, y29, y28, y25, aa29, aa28, aa27, ab29, ab28, ab27 m25_rxd[9:0] input w/ pullu p receive data bit [9:0] t26 m25_tx_en output w/ pullup transmit data enable r26 m25_tx_er output w/ pullup transmit error t27 m25_mtxclk input w/ pull down mii mode transmit clock t25 m25_ txclk output gigabit transmit clock p29 gref_clk0 input w/ pullup gigabit reference clock k25, k26, m25, l26, m26, l25, n26, n25, p26, p25 m26_txd[9:0] output transmit data bit [9:0] f28 m26_rx_dv input w/ pulldown receive data valid g28 m26_rx_er input w/ pullup receive error e25 m26_crs input w/ pulldown carrier sense g29 m26_col input w/ pullup collision detected f29 m26_rxclk input w/ pullup receive clock j27, k29, k28, k27, l29, l28, l27, m29, m28, m27 m26_rxd[9:0] input w/ pullu p receive data bit [9:0] f26 m26_tx_en output w/ pullup transmit data enable e26 m26_tx_er output w/ pullup transmit error f27 m26_mtxclk input w/ pull down mii mode transmit clock f25 m26_ txclk output gigabit transmit clock n29 gref_clk1 input w/ pullup gigabit reference clock led interface c29 led_clk/tstout0 i/o- ts with pull up led serial interface output clock d29 led_syn/tstout1 i/o- ts with pu ll up led output data stream envelope e29 led_bit/tstout2 i/o- ts with pu ll up led serial data output stream b28 g1_rxtx#/tstout3 i/o- ts with pull up led for gigabit port 1 (receive + transmit) c28 g1_dpcol#/tstout4 i/o- ts with pull up led for gigabit port 1 (full duplex + collision) d28 g1_link#/tstout5 i/o- ts with pull up led for gigabit port 1 ball no(s) symbol i/o description ZL50417 data sheet 90 zarlink semiconductor inc. e28 g2_rxtx#/tstout6 i/o- ts with pull up led for gigabit port 2 (receive + transmit) a27 g2_dpcol#/tstout7 i/o- ts with pull up led for gigabit port 2 (full duplex + collision) b27 g2_link#/tstout8 i/o- ts with pull up led for gigabit port 2 c27 init_done/tstout9 i/o- ts with pull up system start operation d27 init_start/tstout1 0 i/o- ts with pull up start initialization c26 checksum_ok/tsto ut11 i/o- ts with pull up eeprom read ok d26 fcb_err/tstout12 i/o- ts with pull up fcb memory self test fail d25 mct_err/tstout13 i/o- ts with pull up mct memory self test fail d24 bist_in_prc/tstout 14 i/o- ts with pull up proc essing memory self test e24 bist_done/tstout1 5 i/o- ts with pull up me mory self test done trunk enable c22 trunk0 input w/ weak internal pull down resistors trunk port enable in unmanaged mode in managed mode doesn't care a21 trunk1 input w/ weak internal pull down resistors trunk port enable in unmanaged mode in managed mode doesn't care b24 trunk2 input w/ weak internal pull down resistors trunk port enable in unmanaged mode in managed mode doesn't care test facility u3, c10 t_mode0, t_mode1 i/o-ts test pins 00 ? test mode ? set mode upon reset, and provides nand tree test output during test mode 01 - reserved - do not use 10 - reserved - do not use 11 ? normal mode. use external pull up for normal mode f3 scan_en input with pull down scan enable 0 - normal mode (open) e27 scanmode input with pull down 1 ? enable test mode 0 - normal mode (open) ball no(s) symbol i/o description ZL50417 data sheet 91 zarlink semiconductor inc. system clock, power, and ground pins e1 sclk input system clock at 100 mhz k12, k13, k17,k18 m10, n10, m20, n20, u10, v10, u20, v20, y12, y13, y17, y18 vdd power +2.5 volt dc supply f13, f14, f15, f16, f17, n6, p6, r6, t6, u6, n24, p24, r24, t24, u24, ad13, ad14, ad15, ad16, ad17 vcc power +3.3 volt dc supply m12, m13, m14, m15, m16, m17, m18, n12, n13, n14, n15, n16, n17, n18, p12, p13, p14, p15, p16, p17, p18, r12, r13, r14, r15, r16, r17, r18, t12, t13, t14, t15, t16, t17, t18, u12, u13, u14, u15, u16, u17, u18, v12, v13, v14, v15, v16, v17, v18, vss power ground ground f1 avcc analog power analog +2.5 volt dc supply d1 agnd analog ground analog ground misc d22 scancol input scans the collision signal of home phy d23 scanclk input/ output clock for scanning home phy collision and link e23 scanlink input link up signal from home phy f2 resin# input reset input g2 resetout# output reset phy ball no(s) symbol i/o description ZL50417 data sheet 92 zarlink semiconductor inc. ac29, ae28, aj27, af27, aj25 , af24, ah23, ae19, ac27, af29, ag27, af26, ag25, ag23, af23, ag21, ac28, af28, ah27, ae27, ah25, ae24, af22, af20, ad29, ag28, aj26, ae26, aj24, ae23, aj22, aj20, ad27, ah28, ag26, ae25, ag24, ae22, aj23, ag20, ad28, ag29, ah26, af25, ah24, ag22, ah22, ae17, g27, h29, h28, h27, j29, j28, u26, u25, v26, v25, w26, w25, g26, g25, h26, h25, j26, j25, u27, v29, v28, v27, w29, w28, b22, a22, c23, b23, a23, c24, e20, b25 reserved na reserved pins. leave unconnected. bootstrap pins (default = pull up, 1= pull up 0= pull down) after reset tstout0 to tstou15 are used by the led interface. c29 tstout0 default 1 giga link polarity 0 ? active low 1 ? active high d29 tstout1 default 1 rmii mac power saving enable 0 ? no power saving 1 ? power saving e29 tstout2 default 1 recommend disable (0) with pull-down giga half duplex support 0 - disable 1 - enable b28 tstout3 default 1 module detect enable 0 ? hot swap enable 1 ? hot swap disable c28 tstout4 reserved d28 tstout5 default 1 scan speed: ? sclk or sclk 0 ? ? sclk (hpna) 1 - sclk e28 tstout6 reserved ball no(s) symbol i/o description ZL50417 data sheet 93 zarlink semiconductor inc. a27 tstout7 default 1 memory size 0 - 256 k x 32 or 256 k x 64 (4 m total) 1 - 128 k x 32 or 128 k x 64 (2 m total) b27 tstout8 default 1 eeprom installed 0 ? eeprom installed 1 ? eeprom not installed c27 tstout9 default 1 mct aging 0 ? mct aging disable 1 ? mct aging enable d27 tstout10 default 1 fcb aging 0 - fcb aging disable 1 ? fcb aging enable c26 tstout11 default 1 timeout reset 0 ? time out reset disable 1 ? time out reset enable. issue reset if any state machine did not go back to idle for 5 sec. d26 tstout12 reserved d25 tstout13 default 1 fdb ram depth (1 or 2 layers) 0 ? 2 layer 1 ? 1 layer d24 tstout14 reserved e24 tstout15 default 1 sram test mode 0 ? enable test mode 1 ? normal operation t26, r26 g0_txen, g0_txer default: pcs giga0 mode: g0_txen g0_txer 0 0 mii 0 1 rsvd 1 0 gmii 1 1 pcs f26, e26 g1_txen, g1_txer default: pcs giga1 mode: g1_txen g1_txer 0 0 mii 0 1 rsvd 1 0 gmii 1 1 pcs ball no(s) symbol i/o description ZL50417 data sheet 94 zarlink semiconductor inc. note: : ae20, aj18, aj21, aj16, aj14, ae14, aj12, ae11, aj10, aj8, ae8, aj6, ae5, aj4, ag1, ae1, m[15:0]_txen default: rmii 0 ? gpsi 1 - rmii c21 p_d must be pulled-down reserved - must be pulled- down c19, b19, a19 oe_clk[2:0] def ault: 111 programmable delay for internal oe_clk from sclk input. the oe_clk is used for generating the oe0 and oe1 signals. suggested value is 011. c20, b20, a20 la_clk[2:0] def ault: 111 programmable delay for la_clk and lb_clk from internal oe_clk. the la_clk and lb_clk delay from sclk is the sum of the delay programmed in here and the delay in p_d[15:13]. suggested value is 011. # = active low signal input = input signal in-st = input signal with schmitt-trigger output = output signal (tri-state driver) out-od= output signal with open-drain driver i/o-ts = input & output signal with tri-state driver i/o-od = input & output signal with open-drain driver ball no(s) symbol i/o description ZL50417 data sheet 95 zarlink semiconductor inc. 14.2 ball signal name ball no. signal name ball no. si gnal name ball no. signal name d20 la_d[63] d3 la_d[19] a9 la_oe0# b21 la_d[62] e3 la_d[18] b9 la_oe1# d19 la_d[61] d2 la_d[17] f4 lb_d[63] e19 la_d[60] e2 la_d[16] f5 lb_d[62] d18 la_d[59] a7 la_d[15] g4 lb_d[61] e18 la_d[58] b7 la_d[14] g5 lb_d[60] d17 la_d[57] a6 la_d[13] h4 lb_d[59] e17 la_d[56] b6 la_d[12] h5 lb_d[58] d16 la_d[55] c6 la_d[11] j4 lb_d[57] e16 la_d[54] a5 la_d[10] j5 lb_d[56] d15 la_d[53] b5 la_d[9] k4 lb_d[55] e15 la_d[52] c5 la_d[8] k5 lb_d[54] d14 la_d[51] a4 la_d[7] l4 lb_d[53] e14 la_d[50] b4 la_d[6] l5 lb_d[52] d13 la_d[49] c4 la_d[5] m4 lb_d[51] e13 la_d[48] a3 la_d[4] m5 lb_d[50] d21 la_d[47] b3 la_d[3] n4 lb_d[49] e21 la_d[46] c3 la_d[2] n5 lb_d[48] a18 la_d[45] b2 la_d[1] g3 lb_d[47] b18 la_d[44] c2 la_d[0] h1 lb_d[46] c18 la_d[43] c14 la_a[20] h2 lb_d[45] a17 la_d[42] a13 la_ a[19] h3 lb_d[44] b17 la_d[41] b13 la_ a[18] j1 lb_d[43] c17 la_d[40] c13 la_a[17] j2 lb_d[42] a16 la_d[39] a12 la_ a[16] j3 lb_d[41] b16 la_d[38] b12 la_ a[15] k1 lb_d[40] c16 la_d[37] c12 la_a[14] k2 lb_d[39] a15 la_d[36] a11 la_ a[13] k3 lb_d[38] b15 la_d[35] b11 la_ a[12] l1 lb_d[37] c15 la_d[34] c11 la_a[11] l2 lb_d[36] ZL50417 data sheet 96 zarlink semiconductor inc. a14 la_d[33] d11 la_ a[10] l3 lb_d[35] b14 la_d[32] e11 la_a[9] m1 lb_d[34] d9 la_d[31] a10 la_a[8] m2 lb_d[33] e9 la_d[30] b10 la_a[7] m3 lb_d[32] d8 la_d[29] d10 la_a[6] u4 lb_d[31] e8 la_d[28] e10 la_a[5] u5 lb_d[30] d7 la_d[27] a8 la_a[4] v4 lb_d[29] e7 la_d[26] c7 la_a[3] v5 lb_d[28] d6 la_d[25] b8 la_dsc# w4 lb_d[27] e6 la_d[24] c1 la_clk w5 lb_d[26] d5 la_d[23] c9 la_we# y4 lb_d[25] e5 la_d[22] d12 la_we0# y5 lb_d[24] d4 la_d[21] e12 la_we1# aa4 lb_d[23] e4 la_d[20] c8 la_oe# aa5 lb_d[22] ab4 lb_d[21] u2 lb_oe1# ah7 m[4]_rxd[0] ab5 lb_d[20] r28 mdc ae6 m[3]_rxd[0] ac4 lb_d[19] p28 mdio ah5 m[2]_rxd[0] ac5 lb_d[18] r29 m_clk ah2 m[1]_rxd[0] ad4 lb_d[17] ac29 nc af2 m[0]_rxd[0] ad5 lb_d[16] ae28 nc ac27 nc w1 lb_d[15] aj27 nc af29 nc y1 lb_d[14] af27 nc ag27 nc y2 lb_d[13] aj25 nc af26 nc y3 lb_d[12] af24 nc ag25 nc aa1 lb_d[11] ah23 nc ag23 nc aa2 lb_d[10] ae19 nc af23 nc aa3 lb_d[9] af21 m[15]_rxd[1] ag21 nc ab1 lb_d[8] aj19 m[14]_rxd[1] ah21 m[15]_crs_dv ab2 lb_d[7] af18 m[13]_rxd[1] af19 m[14]_crs_dv ab3 lb_d[6] aj17 m[12]_rxd[1] af17 m[13]_crs_dv ac1 lb_d[5] aj15 m[11]_rx d[1] ag17 m[12]_crs_dv ball no. signal name ball no. si gnal name ball no. signal name ZL50417 data sheet 97 zarlink semiconductor inc. ac2 lb_d[4] af15 m[10]_rx d[1] ag15 m[11]_crs_dv ac3 lb_d[3] aj13 m[9]_rxd[1] af14 m[10]_crs_dv ad1 lb_d[2] af12 m[8]_r xd[1] ag13 m[9]_crs_dv ad2 lb_d[1] aj11 m[7]_r xd[1] af11 m[8]_crs_dv ad3 lb_d[0] aj9 m[6]_rxd[1] ag11 m[7]_crs_dv n3 lb_a[20] af9 m[5]_rxd[1] ag9 m[6]_crs_dv n2 lb_a[19] aj7 m[4]_rxd[1] af8 m[5]_crs_dv n1 lb_a[18] af6 m[3]_rxd[1] ag7 m[4]_crs_dv p3 lb_a[17] aj5 m[2]_rxd[1] af5 m[3]_crs_dv p2 lb_a[16] aj3 m[1]_rxd[1] ag5 m[2]_crs_dv p1 lb_a[15] af1 m[0]_rxd[1] ah3 m[1]_crs_dv r5 lb_a[14] ac28 nc af3 m[0]_crs_dv r4 lb_a[13] af28 nc ad29 nc r3 lb_a[12] ah27 nc ag28 nc r2 lb_a[11] ae27 nc aj26 nc r1 lb_a[10] ah25 nc ae26 nc t5 lb_a[9] ae24 nc aj24 nc t4 lb_a[8] af22 nc ae23 nc t3 lb_a[7] af20 nc aj22 nc t2 lb_a[6] ae21 m[15]_rxd[0] aj20 nc t1 lb_a[5] ah19 m[14]_rxd[0] ae20 m[15]_txen w3 lb_a[4] ah20 m[13]_rxd[0] aj18 m[14]_txen w2 lb_a[3] ah17 m[12]_rxd[0] aj21 m[13]_txen v1 lb_adsc# ah15 m[11]_rxd[0] aj16 m[12]_txen g1 lb_clk ae15 m[10]_rxd[0] aj14 m[11]_txen v3 lb_we# ah13 m[9]_r xd[0] ae14 m[10]_txen p4 lb_we0# ae12 m[8]_ rxd[0] aj12 m[9]_txen p5 lb_we1# ah11 m[7]_rxd[0] ae11 m[8]_txen v2 lb_oe# ah9 m[6]_rx d[0] aj10 m[7]_txen u1 lb_oe0# ae9 m[5]_r xd[0] aj8 m[6]_txen ae8 m[5]_txen ah8 m[6]_txd[0] g27 reserved ball no. signal name ball no. si gnal name ball no. signal name ZL50417 data sheet 98 zarlink semiconductor inc. aj6 m[4]_txen af7 m[5]_txd[0] h29 reserved ae5 m[3]_txen ah6 m[4]_txd[0] h28 reserved aj4 m[2]_txen af4 m[3]_txd[0] h27 reserved ag1 m[1]_txen ah4 m[2]_txd[0] j29 reserved ae1 m[0]_txen ag2 m[1]_txd[0] j28 reserved ad27 nc ae2 m[0]_txd[0] j27 m26_rxd[9] ah28 nc u26 reserved k29 m26_rxd[8] ag26 nc u25 reserved k28 m26_rxd[7] ae25 nc v26 reserved k27 m26_rxd[6] ag24 nc v25 reserved l29 m26_rxd[5] ae22 nc w26 reserved l28 m26_rxd[4] aj23 nc w25 reserved l27 m26_rxd[3] ag20 nc y27 m25_txd[9] m29 m26_rxd[2] ae18 m[15]_txd[1] y26 m25_txd[8] m28 m26_rxd[1] ag18 m[14]_txd[1] aa26 m25_txd[7] m27 m26_rxd[0] ae16 m[13]_txd[1] aa25 m25_txd[6] g26 reserved ag16 m[12]_txd[1] ab26 m25_txd[5] g25 reserved ag14 m[11]_txd[1] ab25 m25_txd[4] h26 reserved ae13 m[10]_txd[1] ac26 m25_txd[3] h25 reserved ag12 m[9]_txd[1] ac25 m25_txd[2] j26 reserved ae10 m[8]_txd[1] ad26 m25_txd[1] j25 reserved ag10 m[7]_txd[1] ad25 m25_txd[0] k25 m26_txd[9] ag8 m[6]_txd[1] u27 reserved k26 m26_txd[8] ae7 m[5]_txd[1] v29 reserved m25 m26_txd[7] ag6 m[4]_txd[1] v28 reserved l26 m26_txd[6] ae4 m[3]_txd[1] v27 reserved m26 m26_txd[5] ag4 m[2]_txd[1] w29 reserved l25 m26_txd[4] ag3 m[1]_txd[1] w28 reserved n26 m26_txd[3] ae3 m[0]_txd[1] w27 m25_rxd[9] n25 m26_txd[2] ad28 nc y29 m25_rxd[8] p26 m26_txd[1] ag29 nc y28 m25_rxd[7] p25 m26_txd[0] ball no. signal name ball no. si gnal name ball no. signal name ZL50417 data sheet 99 zarlink semiconductor inc. ah26 nc y25 m25_rxd[6] f28 m26_rx_dv af25 nc aa29 m25_rxd[5] g28 m26_rx_er ah24 nc aa28 m25_rxd[4] e25 m26_crs ag22 nc aa27 m25_rxd[3] g29 m26_col ah22 nc ab29 m25_rxd[2] f29 m26_rxclk ae17 nc ab28 m25_rxd[1] f26 m26_tx_en ag19 m[15]_txd[0] ab27 m25_rxd[0] e26 m26_tx_er ah18 m[14]_txd[0] r26 m25_tx_er f25 m26_txclk af16 m[13]_txd[0] t25 m25_txclk e24 bist_done/tstout[15] ah16 m[12]_txd[0] t26 m25_tx_en d24 bist_in_prc/tst0ut[14] ah14 m[11]_txd[0] t28 m25_rx_dv d25 mct_err/tstout[13] af13 m[10]_txd[0] u28 m25_rx_er d26 fcb_err/tstout[12] ah12 m[9]_txd[0] r25 m25_crs c26 checksum_ok/tstout[11] af10 m[8]_txd[0] u29 m25_col d27 init_start/tstout[10] ah10 m[7]_txd[0] t29 m25_rxclk c27 init_done/tstout[9] b27 g2_link#/tstout[8] u18 vss n12 vss a27 g2_dpcol#/tstout[7] v12 vss n13 vss e28 g2_rxtx#/tstou t[6] v13 vss k17 vdd d28 g1_link#/tstout[5] v14 vss k18 vdd c28 g1_dpcol#/tstout[4] v15 vss m10 vdd b28 g1_rxtx#/tstou t[3] v16 vss n10 vdd e29 led_bit/tstout[2] v17 vss m20 vdd d29 led_syn/tstout[1] v18 vss n20 vdd c29 led_clk/tstout[0] n14 vss u10 vdd n29 gref_clk1 n15 vss v10 vdd p29 gref_clk0 n16 vss u20 vdd f3 scan_en n17 vss v20 vdd e1 sclk n18 vss y12 vdd u3 t_mode0 p12 vss y13 vdd c10 t_mode1 p13 vss y17 vdd b24 trunk2 p14 vss y18 vdd ball no. signal name ball no. si gnal name ball no. signal name ZL50417 data sheet 100 zarlink semiconductor inc. a21 trunk1 p15 vss k12 vdd c22 trunk0 p16 vss k13 vdd a26 strobe c19 oe_clk2 m16 vss b26 d0 b19 oe_clk1 m17 vss c25 autofd a19 oe_clk0 m18 vss a24 scl r13 vss f16 vcc a25 sda r14 vss f17 vcc f1 avcc r15 vss n6 vcc d1 agnd r16 vss p6 vcc d22 scancol r17 vss r6 vcc e23 scanlink r18 vss t6 vcc e27 scanmode t12 vss u6 vcc n28 t13 vss n24 vcc n27 t14 vss p24 vcc f2 resin# t15 vss r24 vcc g2 resetout# t16 vss t24 vcc b22 reserved t17 vss u24 vcc a22 reserved t18 vss ad13 vcc c23 reserved u12 vss ad14 vcc b23 reserved u13 vss ad15 vcc a23 reserved u14 vss ad16 vcc c24 reserved u15 vss ad17 vcc d23 scanclk u16 vss f13 vcc t27 m25_mtxclk u17 vss f14 vcc f27 m26_mtxclk m12 vss f15 vcc c20 la_clk2 m13 vss b20 la_clk1 m14 vss a20 la_clk0 m15 vss c21 p_d p17 vss e20 reserved p18 vss b25 reserved r12 vss ball no. signal name ball no. si gnal name ball no. signal name ZL50417 data sheet 101 zarlink semiconductor inc. 14.3 ac/dc timing 14.3.1 absolute maximum ratings storage temperature -65c to +150c operating temperature -40 o c to + 85 o c maximum junction temperature +125 c supply voltage vcc with respect to v ss +3.0 v to +3.6 v supply voltage vdd with respect to v ss +2.38 v to +2.75 v voltage on input pins -0.5 v to (vcc + 3.3 v) caution: stress above those listed may damage the device. exposure to the absolute maximum ratings for extended periods may affect device reliability. functi onality at or above these limits is not implied. 14.3.2 dc electrical characteristics vcc = 3.0 v to 3.6 v (3.3v +/- 10%)t ambient = -40 c to +85 c vdd = 2.5 v +10% - 5% 14.3.3 recommended operating conditions symbol parameter description min. typ. max. unit f osc frequency of operation 100 mhz i cc supply current ? @ 100 mhz (vcc=3.3 v) 350 ma i dd supply current ? @ 100 mhz (vdd =2.5 v) 1400 ma v oh output high voltage (cmos) 2.4 v v ol output low voltage (cmos) 0.4 v v ih-ttl input high voltage (ttl 5 v tolerant) 2.0 vcc + 2.0 v v il-ttl input low voltage (ttl 5 v tolerant) 0.8 v i il input leakage current (0.1 v < v in < vcc) (all pins except those with internal pull-up/pull- down resistors) 10 a i ol output leakage current (0.1 v < vout < vcc) 10 a c in input capacitance 5 pf c out output capacitance 5 pf c i/o i/o capacitance 7 pf ja thermal resistance with 0 air flow 11.2 c/w ja thermal resistance with 1 m/s air flow 10.2 c/w ja thermal resistance with 2 m/s air flow 8.9 c/w ZL50417 data sheet 102 zarlink semiconductor inc. 14.3.4 typical reset & bootstrap timing diagram figure 17 - typical reset & bootstrap timing diagram jc thermal resistance between junction and case. 3.1 c/w jb thermal resistance between junction and board. 6.6 c/w symbol paramete rmin.typ. note r1 delay until resetou t# is tri-stated 10 ns resetou t# state is then determined by the external pull-up/down resistor r2 bootstrap stabilization 1 s10 s bootstrap pins sampled on rising edge of resin# a a. the tstout[8:0] pins will switch over to the led interface functionality in 3 sclk cycles after resin# goes high r3 resetout# assertion 2 ms table 12 - reset & bootstrap timing symbol parameter description min. typ. max. unit resetout# tri-stated resin# r1 r2 r3 bootstrap pins inputs outputs outputs ZL50417 data sheet 103 zarlink semiconductor inc. 14.4 local frame buff er sbram memory interface 14.4.1 local sbram memory interface figure 18 - local memory interface ? input setup and hold timing figure 19 - local memory interface - output valid delay timing l1 l2 la_clk la_d[63:0] l3-min l3-max l4-min l4-max l6-min l6-max l7-min l7-max l8-min l8-max la_clk la_d[63:0] la_a[20:3] la_adsc# la_we[1:0]# #### la_oe[1:0]# l9-min l9-max la_we# l10-min l10-max la_oe# ZL50417 data sheet 104 zarlink semiconductor inc. 14.5 local switch database sbram memory interface 14.5.1 local sbram memory interface figure 20 - local memory interface ? input setup and hold timing ac characteristics ? local frame buffer sbram memory interface symbol parameter -100 mhz note min. (ns) max. (ns) l1 la_d[63:0] input set-up time 4 l2 la_d[63:0] input hold time 1.5 l3 la_d[63:0] output valid delay 1.5 7 c l = 25 pf l4 la_a[20:3] output valid delay 2 7 c l = 30 pf l6 la_adsc# output valid delay 1 7 c l = 30 pf l7 la_we[1:0]#output valid delay 1 7 c l = 25 pf l8 la_oe[1:0]# output valid delay -1 1 c l = 25 pf l9 la_we# output valid delay 1 7 c l = 25 pf l10 la_oe# output valid delay 1 5 c l = 25 pf l1 l2 lb_clk lb_d[63:0] ZL50417 data sheet 105 zarlink semiconductor inc. figure 21 - local memory interface - output valid delay timing ac characteristics ? local switch database sbram memory interface symbol parameter -100 mhz note min. (ns) max. (ns) l1 lb_d[63:0] input set-up time 4 l2 lb_d[63:0] input hold time 1.5 l3 lb_d[63:0] output valid delay 1.5 7 c l = 25 pf l4 lb_a[20:3] output valid delay 2 7 c l = 30 pf l6 lb_adsc# output valid delay 1 7 c l = 30 pf l8 lb_we[1:0]#output valid delay 1 7 c l = 25 pf l9 lb_oe[1:0]# output valid delay -1 1 c l = 25 pf l10 lb_we# output valid delay 1 7 c l = 25 pf l11 lb_oe# output valid delay 1 5 c l = 25 pf l3-min l3-max l4-min l4-max l6-min l6-max l8-min l8-max l9-min l9-max l10-min l10-max lb_clk lb_d[31:0] lb_a[21:2] lb_adsc# lb_we[1:0]# lb_oe[1:0]# lb_we# l11-min l11-max lb_oe# ZL50417 data sheet 106 zarlink semiconductor inc. 14.6 ac characteristics 14.6.1 reduced media independent interface figure 22 - ac characteristics ? reduced media independent interface figure 23 - ac characteristics ? reduced media independent interface ac characteristics ? reduced media independent interface symbol parameter -50 mhz note min. (ns) max. (ns) m2 m[15:0]_rxd[1:0] input setup time 4 m3 m[15:0]_rxd[1:0] input hold time 1 m4 m[15:0]_crs_dv input setup time 4 m5 m[15:0]_crs_dv input hold time 1 m6 m[15:0]_txen output delay time 2 11 c l = 20 pf m7 m[15:0]_txd[1:0] output delay time 2 11 c l = 20 pf m6-min m6-max m7-min m7-max m_clki m[23:0]_txen m[23:0] _txd[1:0] 15 15 m2 m_clki m[23:0]_rxd m[23:0]_crs_dv m3 m4 m5 15 15 ZL50417 data sheet 107 zarlink semiconductor inc. 14.6.2 gigabit media independent interface - port a figure 24 - ac characteristics- gmii figure 25 - ac characteristics ? gigabit media independent interface g12-min g12-max g13-min g13-max g14-min g14-max m25_txclk m25_txd [15:0] m25_tx_en] m25_tx_er [7:0] m25_rxclk g1 g2 m25_rxd[15:0] g3 g4 m25_rx_dv g5 g6 m25_rx_er g7 g8 m25_rx_crs [7:0] ZL50417 data sheet 108 zarlink semiconductor inc. 14.6.3 ten bit interface - port a figure 26 - gigabit tbi interface transmit timing figure 27 - gigabit tbi interface receive timing ac characteristics ? gigabit media independent interface symbol parameter -125 mhz note min. (ns) max. (ns) g1 m[25]_rxd[7:0] input setup times 2 g2 m[25]_rxd[7:0] input hold times 1 g3 m[25]_rx_dv input setup times 2 g4 m[25]_rx_dv input hold times 1 g5 m[25]_rx_er input setup times 2 g6 m[25]_rx_er input hold times 1 g7 m[25]_crs input setup times 2 g8 m[25]_crs input hold times 1 g12 m[25]_txd[7:0] output delay times 1 6 c l = 20 pf g13 m[25]_tx_en output delay times 1 6.5 c l = 20 pf g14 m[25]_tx_er output delay times 1 6 c l = 20 pf symbol parameter min. (ns) max. (ns) note t1 m25_txd[9:0] output delay time 1 6 c l = 20 pf table 13 - output delay timing m25_txclk m25_txd [9:0] timin timax m25_rxclk m25_col t2 m25_rxd[9:0] t3 t2 t3 ZL50417 data sheet 109 zarlink semiconductor inc. 14.6.4 gigabit media independent interface - port b figure 28 - ac characteristics- gmii figure 29 - ac characteristics ? gigabit media independent interface symbol paramete r min. (ns) max. (ns) note t2 m25_rxd[9:0] input setup time 3 t3 m25_rxd[9:0] input hold time 3 table 14 - input setup timing g12-min g12-max g13-min g13-max g14-min g14-max m26_txclk m26_txd [15:0] m26_tx_en] m26_tx_er [7:0] m26_rxclk g1 g2 m26_rxd[15:0] g3 g4 m26_rx_dv g5 g6 m26_rx_er g7 g8 m26_rx_crs [7:0] ZL50417 data sheet 110 zarlink semiconductor inc. 14.6.5 ten bit interface - port b figure 30 - gigabit tbi interface transmit timing figure 31 - gigabit tbi interface timing ac characteristics ? gigabit media independent interface symbol parameter -125 mhz note min. (ns) max. (ns) g1 m[26]_rxd[7:0] input setup times 2 g2 m[26]_rxd[7:0] input hold times 1 g3 m[26]_rx_dv input setup times 2 g4 m[26]_rx_dv input hold times 1 g5 m[26]_rx_er input setup times 2 g6 m[26]_rx_er input hold times 1 g7 m[26]_crs input setup times 2 g8 m[26]_crs input hold times 1 g12 m[26]_txd[7:0] ou tput delay times 1 6 c l = 20 pf g13 m[26]_tx_en output delay times 1 6.5 c l = 20 pf g14 m[26]_tx_er output delay times 1 6 c l = 20 pf m26_txclk m26_txd [9:0] timin timax m26_rxclk m26_col t2 m26_rxd[9:0] t3 t2 t3 ZL50417 data sheet 111 zarlink semiconductor inc. 14.6.6 led interface figure 32 - ac characteristics ? led interface symbol parameter min. (ns) max. (ns) note t1 m26_txd[9:0] output delay time 1 6 c l = 20 pf table 15 - output delay timing symbol parameter min. (ns) max. (ns) note t2 m26_rxd[9:0] input setup time 3 t3 m26_rxd[9:0] in put hold time 3 table 16 - input setup timing symbol parameter variable freq. note: min. (ns) max. (ns) le5 led_syn output valid delay -1 7 c l = 30 pf le6 led_bit output valid delay -1 7 c l = 30 pf table 17 - ac characteristics ? led interface le5-min le5-max le6-min le6-max led_clk led_syn led_bit ZL50417 data sheet 112 zarlink semiconductor inc. 14.6.7 scanlink scancol output delay timing figure 33 - scanlink scancol output delay timing figure 34 - scanlink, scancol setup timing symbol parameter -25 mhz note min. (ns) max. (ns) c1 scanlink input set-up time 20 c2 scanlink input hold time 2 c3 scancol input setup time 20 c4 scancol input hold time 1 c5 scanlink output valid delay 0 10 c l = 30 pf c7 scancol output valid delay 0 10 c l = 30 pf table 18 - scanlink, scancol timing c5-min c5-max c7-min c7-max scanclk scanlink scancol scanclk c1 c2 scanlink c3 c4 scancol ZL50417 data sheet 113 zarlink semiconductor inc. 14.6.8 mdio input setup and hold timing figure 35 - mdio input setup and hold timing figure 36 - mdio output delay timing symbol parameter 1mhz note min. (ns) max. (ns) d1 mdio input setup time 10 d2 mdio input hold time 2 d3 mdio output delay time 1 20 c l = 50 pf table 19 - mdio timing mdc d1 d2 mdio d3-min d3-max mdc mdio ZL50417 data sheet 114 zarlink semiconductor inc. 14.6.9 i2c input setup timing figure 37 - i2c input setup timing figure 38 - i2c output delay timing symbol parameter 50 khz note min. (ns) max. (ns) s1 sda input setup time 20 s2 sda input hold time 1 s3* sda output delay time 4 usec 6 usec c l = 30 pf * open drain output. low to high transistor is controlled by external pullup resistor. table 20 - i2c timing s1 s2 scl sda s3-min s3-max scl sda ZL50417 data sheet 115 zarlink semiconductor inc. 14.6.10 serial interface setup timing figure 39 - serial interface setup timing figure 40 - serial interface output delay timing symbol parameter min. (ns) max. (ns) note d1 d0 setup time 20 d2 d0 hold time 3 s d3 autofd output delay time 1 50 c l = 100 pf d4 strobe low time 5 s d5 strobe high time 5 s table 21 - serial interface timing strobe d1 d2 d0 d1 d2 d4 d5 d3-min d3-max strobe autofd apprd. issue date acn package code previous package codes: conforms to jedec ms - 034 2.20 e e b e1 dimension d d1 a2 a1 a 1.27 553 max 0.70 2.46 1.17 ref 0.50 min 3. seating plane is defined by the spherical crowns of the solder balls. 1. controlling dimensions are in mm 2. dimension "b" is measured at the maximum solder ball diameter 4. n is the number of solder balls 5. not to scale. note: 0.60 0.90 37.30 37.70 34.50 ref 37.30 37.70 34.50 ref e1 d1 d e e b a2 6. substrate thickness is 0.56 mm www.zarlink.com information relating to products and services furnished herein by zarlink semiconductor inc. or its subsidiaries (collectively ?zarlink?) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from t he application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, u nder patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchasers of products are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or other intellect ual property rights owned by zarlink. this publication is issued to provide information only and (unless agreed by zarlink in writing) may not be used, applied or re produced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user?s responsibility t o fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not b een superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to zarlink?s conditi ons of sale which are available on request. purchase of zarlink?s i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in and i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright zarlink semiconductor inc. all rights reserved. technical documentation - not for resale for more information about all zarlink products visit our web site at |
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